Mail Index

• Thread Index

• [openrisc]
  • From: "Mark Barr" <mrbarr@charter.net>
• Re: [openrisc] Can gdb for or1k read/write the address of WISHBONE SOC bus ?
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Can gdb for or1k read/write the address of WISHBONE SOC bus ?
  • From: "Zhangyong" <zhangyong@nari-relays.com>
• Re: [openrisc] Is the or1ksim not able to the mem_ctrl power-on boot?
  • From: Simon Srot <simons@opencores.org>
• Re: [openrisc] Can gdb for or1k read/write the address of WISHBONE SOC bus ?
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] The documention of or1ksim/gdb is few!
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] How to use gdb set connamd ?
  • From: "Zhangyong" <zhangyong@nari-relays.com>
• [openrisc] Can gdb for or1k read/write the address of WISHBONE SOC bus ?
  • From: "Zhangyong" <zhangyong@nari-relays.com>
• [openrisc] The documention of or1ksim/gdb is few!
  • From: "Zhangyong" <zhangyong@nari-relays.com>
• [openrisc] Is the or1ksim not able to the mem_ctrl power-on boot?
  • From: "Zhangyong" <zhangyong@nari-relays.com>
• RE: [openrisc] Re: JTAG Proxy
  • From: "Igor Mohor" <igorm@opencores.org>
• [openrisc] Re: JTAG Proxy
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Question on breakpoint method
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Question on breakpoint method
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Question on breakpoint method
  • From: maunal moren <maunal02@yahoo.com>
• Re: [openrisc] Problem about configure the gcc with "--target=or32-uclinux"
  • From: Ivan Guzvinec <ivang@opencores.org>
• Re: [openrisc] DSP instruccions fail
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Breakpoints + Development interface
  • From: Marko Mlinar <markom@opencores.org>
• RE: [openrisc] Breakpoints + Development interface
  • From: "Igor Mohor" <igorm@opencores.org>
• [openrisc] Breakpoints + Development interface
  • From: "Luis Santos" <lsantos@mail.isec.pt>
• Re: [openrisc] Problem about configure the gcc with "--target=or32-uclinux"
  • From: Ivan Guzvinec <ivang@opencores.org>
• [openrisc] DSP instruccions fail
  • From: "JCastillo" <javier_castillo_villar@yahoo.es>
• Re: [openrisc] DSP instructions assembler error
  • From: "JCastillo" <javier_castillo_villar@yahoo.es>
• Re: [openrisc] DSP instructions assembler error
  • From: "xxxx" <meleth_esp@yahoo.es>
• Re: [openrisc] DSP instructions assembler error
  • From: "xxxx" <meleth_esp@yahoo.es>
• Re: [openrisc] DSP instructions assembler error
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] DSP instructions assembler error
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] DSP instructions assembler error
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] DSP instructions assembler error
  • From: javier_castillo_villar@yahoo.es
• Re: [openrisc] Problem about configure the gcc with "--target=or32-uclinux"
  • From: xu hu <giro_cn@yahoo.com>
• [openrisc] Problem about configure the gcc with "--target=or32-uclinux"
  • From: xu hu <giro_cn@yahoo.com>
• [openrisc] DSP instructions
  • From: javier_castillo_villar@yahoo.es
• Re: [openrisc] Error compiling binutils
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Help on compilation with or32-uclinux-gcc
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Error compiling binutils
  • From: javier_castillo_villar@yahoo.es
• [openrisc] Help on compilation with or32-uclinux-gcc
  • From: maunal moren <maunal02@yahoo.com>
• Re: [openrisc] Simulator as a debuger
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Error compiling binutils
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Error compiling binutils
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Gdb Debuginfo for variables in the data-segment
  • From: Andreas Rasmusson <ara@voxi.se>
• [openrisc] Error compiling binutils
  • From: javier_castillo_villar@yahoo.es
• Re: [openrisc] How to simulate OpenRisc in ModelSim
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] How to simulate OpenRisc in ModelSim
  • From: Xing Yu <x.yu@ee.qub.ac.uk>
• Re: [openrisc] Gdb Debuginfo for variables in the data-segment
  • From: Gili Gamliel <gilig@flextronics.co.il>
• Re: [openrisc] Simulator as a debuger
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Gdb Debuginfo for variables in the data-segment
  • From: Andreas Rasmusson <ara@voxi.se>
• Re: [openrisc] Simulator as a debuger
  • From: Gili Gamliel <gilig@flextronics.co.il>
• Re: [openrisc] or1200_defines.v bug?
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] or1200_defines.v bug?
  • From: Jeff Hanoch <jeff@lowrance.com>
• Re: [openrisc] Simulator as a debuger
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Simulator as a debuger
  • From: Gili Gamliel <gilig@flextronics.co.il>
• Re: [openrisc] did the uclinux support loading program from JTAG port?
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] did the uclinux support loading program from JTAG port?
  • From: "mtsu" <taylor@pictologic.com>
• [openrisc] 坐以待斃不如把握機會
  • From: real@h8h.com.tw
• Re: [openrisc] gdb over jtag requirements?
  • From: Simon Srot <simons@opencores.org>
• Re: [openrisc] who can run the uclinux successfully?
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: maunal moren <maunal02@yahoo.com>
• Re: [openrisc] who can run the uclinux successfully?
  • From: Simon Srot <simons@opencores.org>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: Simon Srot <simons@opencores.org>
• [openrisc] who can run the uclinux successfully?
  • From: "mtsu" <taylor@pictologic.com>
• [openrisc] gdb over jtag requirements?
  • From: Andreas Rasmusson <ara@voxi.se>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: maunal moren <maunal02@yahoo.com>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: maunal moren <maunal02@yahoo.com>
• [openrisc] or1200_defines.v bug?
  • From: Jeff Hanoch <jeff@lowrance.com>
• Re: [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] or32-uclinux, or32-uclibc and or1ksim
  • From: maunal moren <maunal02@yahoo.com>
• Re: [openrisc] connecting GDB to remote target
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] connecting GDB to remote target
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Question about or1ksim with gdb
  • From: Marko Mlinar <markom@opencores.org>