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Hello, I'm new at OpenRISC
list and I'm not an expert on Verilog. While searching on the
OpenRISC(OR) docs, FAQ, previous messages and also Verilog code (hard work) I
have no success on getting definitive answers to the questions I present below.
I'll appreciate very much your support. From the OR1200 (old)
documentation and from the source code I conclude that this specific
implementation of OR1000 architecture hasn't already watchpoint/breakpoint
support (special purpose registers DVR[0-7] & DCR[0-7] ). On pg.
47 of "or1200_spec.pdf" we found the following information: "DMR2[WGB] bits
specify which watchpoints invoke breakpoint exception". I become confused
because DMR2 register works with the DVR & DCR pairs. 1- Does the actual
OR1200 implementation has any programmable way (named breakpoint or not) to
freeze the processor at any time and/or on any instruction? I'm not interested
on approaches that halt the processor using a special instruction. I really need
to stop it during the normal flow, without previously inserting special
instructions in the middle. 2- Does the solution to 1)
allows us to get the processor control through its development interface? How
the outside world is notified about such event? 3- Does the current OR1200
implementation follows the recent "SoC/OpenRISC Development Interface" from
Igor? 4- Does anyone can point me
a processor/ASIC (open source or not) that has breakpoint support and a
development interface (On Chip Debugging) based on IEEE 1149.1 JTAG similar
to the one Igor specifies, with rich internal scan-chains? (I know that Atmel
has an ERC32 variant named TSC695E but ... it is very expensive and the core
isn't open sourced. Motorola also use the same OCD method on the PowerPC. Unfortunately,
in this case the internal scan chain information is only provided to
Emulator vendors under a NDA.) Thanks for your time and
feedback, Luís Santos |