Re: [openrisc] problems with or1ksim

[javier_castillo_villar@yahoo.es]

Hi:

I correct the problem. I was using the default sim.cfg and it use MMU. I 
deactivate MMU and it works.

Thanks

----- Original Message ----- 
From: Marko Mlinar <markom@o... > 
To: openrisc@o...  
"Simons@O... " <simons@o... > 
Date: Mon, 21 Oct 2002 15:47:19 +0200 
Subject: Re: [openrisc] problems with or1ksim 

> 
> 
> I don't think this is the same bug, but it is known bug with MC and 
> cache, 
> I think it only happens if you configure MC incorrectly. 
> Simon said he will fix this one, but I suppose he is busy with 
> other things 
> right now. 
> Try enabling the MC. 
> 
> Marko 
> 
> On Monday 21 October 2002 14:43, javier_castillo_villar@y...  
> wrote: 
> > I obtain the same error. 
> > This is the dump: 
> > Reading script file from 'sim.cfg'... 
> > WARNING: config.cpu: Invalid parameter: slp; ignoring. 
> > 
> > WARNING: config.cpu: Invalid parameter: btic; ignoring. 
> > 
> > WARNING: config.cpu: Invalid parameter: bpb; ignoring. 
> > 
> > WARNING: config.uart: Invalid parameter: enabled; ignoring. 
> > 
> > WARNING: config.dma: Invalid parameter: enabled; ignoring. 
> > 
> > WARNING: config.base: Unknown section: tick; ignoring. 
> > WARNING: config.base: Invalid parameter: =; ignoring. 
> > 
> > WARNING: config.base: Invalid parameter: irq; ignoring. 
> > 
> > 
> > Building automata... done, num uncovered: 0/212. 
> > Parsing operands data... done. 
> > loadcode: filename linux  startaddr=0  virtphy_transl=0 
> > Not COFF file format 
> > ELF type: 0x0002 
> > ELF machine: 0x8472 
> > ELF version: 0x00000001 
> > ELF sec = 22 
> > Section: .romvec, vaddr: 0xf0000000, paddr: 0xf0000000, 
> offset: 
> > 0x00001000, size: 0x00000c14 
> > Section: .text, vaddr: 0xf0002000, paddr: 0xf0002000, offset: 
> > 0x00002000, size: 0x0008c014 
> > Section: .rodata, vaddr: 0xf008e014, paddr: 0xf008e014, 
> offset: 
> > 0x0008e014, size: 0x00007b28 
> > Section: .initrd, vaddr: 0xf0095b3c, paddr: 0xf0095b3c, 
> offset: 
> > 0x00095b3c, size: 0x00035c00 
> > Section: .data, vaddr: 0x00002000, paddr: 0xf00cb73c, offset: 
> > 0x000cc000, size: 0x00008bfc 
> > Section: .ramvec, vaddr: 0x00000000, paddr: 0xf00d4338, 
> offset: 
> > 0x000d5000, size: 0x00000c14 
> > WARNING: UART0 has problems with RX file stream. 
> > WARNING: Keyboard has problems with RX file stream. 
> > Resetting PIC. 
> > Resetting memory controller. 
> > EXCEPTION: write out of memory (8-bit access to 90000002) 
> > Violación de segmento (core dumped) 
> > 
> > 
> > ----- Original Message ----- 
> > From: Marko Mlinar <markom@o... > 
> > To: openrisc@o... , Nan Zhou <lavender_uc@y... > 
> > Date: Mon, 21 Oct 2002 08:35:49 +0200 
> > Subject: Re: [openrisc] problems with or1ksim 
> > 
> > > Hi! 
> > > 
> > > I was unable to reconstruct your problem, I have some 
> > > advices below, otherwise please send more detailed bug 
> report. 
> > > 
> > > > WARNING: UARTO has problems with RX file stream. 
> > > > 
> > > > WARNING: Keyboard has problems with RX file system.) 
> > > 
> > > It is possible that lack of uart0.rx or keyboard0.rx 
> files cause 
> > > segmentation 
> > > fault. Please create the files and try if it helps. 
> > > 
> > > > The same problem happened when I ran 
> or32-uclinux-sim from 
> > > > /opt/or32-uclinux/bin/ instead with inputing 
> sim.cfg. But if 
> > > 
> > > sim.cfg is not 
> > > 
> > > > given here, I will get exception and when canceling 
> it, I can 
> > > 
> > > get into 
> > > 
> > > > simulator as (sim). 
> > > 
> > > Also try with sim "exit" and "dhry" binary. 
> > > 
> > > > I got confused why the configuration given in 
> toolchains 
> > > 
> > > instruction page, 
> > > 
> > > > Architectural Simulator page, and the README file 
> are 
> > > 
> > > different. They are: 
> > > > ./configure --target=or32-uclinux 
> --prefix=/opt/or32-uclinux 
> > > > ./configure --target=or32-rtems 
> --prefix=/opt/or32-rtems 
> > > 
> > > Depends on toolchain you have. 
> > > 
> > > > ./configure --target=or32-uclinux 
> > > > 
> > > > respectively. 
> > > > 
> > > > I wonder if there're different simulators for RTL 
> and 
> > > 
> > > architecture level. 
> > > 
> > > > Also, the README mentions there're drhy.or32 test 
> file under 
> > > 
> > > testbench 
> > > 
> > > > directory but I can't find it. 
> > > 
> > > Yes, it was renamed to "dhry", but README was not yet 
> updated. 
> > > 
> > > hope this helps, 
> > > Marko 
> 
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