[openrisc] CID bits and shadow registers

[mbtirado@mundivia.es]

Thank you very much, Marko.
I am not sure what you mean with "normal virtual memory architecture" 
Do you mean an architecture where the OS changes the base pointer of 
the page table with every context change, so we have a different page 
table for every process? Or instead processes can't use the entire 
memory virtual address but only a part?
Apart from these, I have another question that I hope it might be the 
last: żis it possible to implement CID bits (not hardwiring to zero)without 
implementing shadow registers in an OR1000 architecture? As far as I 
have read the manual, it is not clear if CID bits and shadow registers are 
unavoidably together or not.
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