Mail Index

• Thread Index

• [openrisc] xori instruction
  • From: =?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>
• [openrisc] Cache invalidation & synchronization
  • From: Carlos Sanchez de La Lama <csanchez@teisa.unican.es>
• [openrisc]
  • From: "=?koi8-r?B?4sXT08/Oz9cg8c4=?=" <yashka@mailru.com>
• Re: [openrisc] Jump instructions
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] Jump instructions
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Jump instructions
  • From: Carlos Sanchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] Does OR1200 Support GUI Linux
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Does OR1200 Support GUI Linux
  • From: tpeng@attbi.com
• Re: [openrisc] or1ksim exception processing doesn't follow revised architecture
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] or1ksim exception processing doesn't follow revised architecture
  • From: Carlos Sanchez de La Lama <csanchez@teisa.unican.es>
• Re: [openrisc] Caches lock and invalidate
  • From: Javier <javier@teisa.unican.es>
• Re: [openrisc] Caches lock and invalidate
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] Caches lock and invalidate
  • From: javier@teisa.unican.es
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: =?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: =?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: Marko Mlinar <markom@opencores.org>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: =?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>
• Re: [openrisc] OR1200 implementation of l.sb and l.sh
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] OR1200 implementation of l.sb and l.sh
  • From: =?iso-8859-15?q?Mar=EDa=20Bolado?= <mbolado@teisa.unican.es>
• Re: [openrisc] Building tool chain
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Building tool chain
  • From: bdoney@ieee.org
• Re: [openrisc] Building binutils
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Building binutils
  • From: kinanes@tcd.ie
• [openrisc] updated or1k arch manual
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] Function prologue and stack frame
  • From: Marko Mlinar <markom@opencores.org>
• [openrisc] Industrial IP Cores.
  • From: Manuk Shemsyan <s_manuk@freenet.am>
• [openrisc] Open PDA
  • From: Ingo Maindorfer <ingo@liquidcooling.de>
• [openrisc] 新年快樂~給我的好友!!
  • From: Jackie@www.lampret.com
• [openrisc] Control Systems' IP Cores.
  • From: Manuk Shemsyan <s_manuk@freenet.am>
• [openrisc] Instruction code...
  • From: Manuk Shemsyan <s_manuk@freenet.am>
• Re: [openrisc] or1k arch manual
  • From: "Damjan Lampret" <lampret@opencores.org>
• Re: [openrisc] or1k arch manual
  • From: Mohammad@opencores.org
• Re: [openrisc] Interrupt servicing
  • From: lampret@opencores.org
• Re: [openrisc] Non-cacheable sectors
  • From: lampret@opencores.org
• Re: [openrisc] Set flag if .......... than inmediate and GCC
  • From: lampret@opencores.org
• Re: [openrisc] Field CWS in ICCFGR
  • From: lampret@opencores.org
• Re: [openrisc] Field OF64S in CPUCFGR
  • From: lampret@opencores.org
• Re: [openrisc] or1k arch manual
  • From: lampret@opencores.org
• Re: [openrisc] ORPSOC clocking
  • From: "Damjan Lampret" <lampret@opencores.org>
• [openrisc] ORPSOC clocking
  • From: ericbhyap@yahoo.com
• [openrisc] ucLinux and kernel panic
  • From: =?ISO-8859-15?Q?BERTRAND_Jo=EBl?= <joligibus@free.fr>