RE: [fpu] FPU operations

[Jamil Khatib <jamilkhatib75@yahoo.com>]

Hi all,
It is nice to get all these emails, your discussions
have answered most of my questions.

I have few comments:

1. When I said that different operands may need
different clocks to get the result I meant that
special numbers may produce results faster than normal
ones, because they do not need to be addede.......
This apeer in my first suggested flow chart but I
fixed it later. I am going to pass all numbers onm the
same logic and finally I'll decided which one to pass.
The new flow chart is located under fpu site at
./fpu/add2_flow.ps


2. When I asked about contention on the result bus, it
was another way to ask about different execution
speeds of the FPU units. 
For example:
ADDER needs 3 clks
MULTIPLIER needs 4 clks
and a mul instruction is issued on clock before add
inst what will happen on the result. Both add and mul
instructions have to write to the result. as I know
there should be a method to stall the adder, how can
you manage this kind of operations?

3. OK about the comparison status signals we have also
to add zero status but all these comparisons have to
execute in parallel with all instructions.

4. My adder is almost ready and located in the CVS. it
supports Special numbers handling (inf & NaN) and
generates Invalid exception. but still it have to
generate overflow and underflow.

5. Initial synthesis showed that the 32 bit Add
(represented by + operator) which is performed on a
single pipeline is located in the critical path. still
I have to investigate more.

6. I think we should provide SNAN when NAN is one of
the comparison operands but also we should produce
false for this kind of operation. This is even if the
standard does not requier it but it will give the
software more control.


7. Since we are working on HDL coding why do not we
agree on the same structure and code it and have one
in VHDL and one in verilog. ( as I remmber OR1K was
written in VHDL is there any plans for writing it in
verilog?)


8. I am going to modify the flow charts, block
diagrams and the design document soon according to
these discussions


Regards
Jamil Khatib



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