Attached are 3 files: (Sorry can't get CVS to work ...) a) Updated FASU block (Floating Point Add/Sub Unit) b) New FMUL block (Floating Point Multiply) c) fpu.pdf - a small document describing the blocks All code is written in VERILOG, and is Single Precision Floating Point format, per IEEE 754. Divide block is next ! Comets, suggestions ? Cheers ! rudi