4. Scope of Usage

4. 1. Introduction

The purpose of this chapter is to provide a user of HITAS with guidelines as to the type of circuits on which tool can be used.

In essence, the HITAS static timing analysis platform is designed for digital custom designs and can handle most techniques used in very high speed or low power designs. HITAS is not, however, designed to cope automatically with analog or structures.

For many designers and CAD teams using advanced design techniques, the distinction between analog and digital is not always clearly defined. The role of this chapter is to define what is digital and what is analog for HITAS.

In order to achieve this we first describe the basic assumptions made by HITAS. If these assumptions are not valid for a circuit structure then this is probably analog. In the next section we provide illustrations of a number of different Digital and Custom Digital structures that HITAS is capable of handling. In the final section we present a selection of typical analog structures for which HITAS, in its native mode, is not suited. However, the tool provides means to link with analog simulators, in order to handle those analog structures.

4. 2. HITAS Basic Assumptions

4. 2. 1. Circuit Partitioning

The circuit partitioning in HITAS is based on the identification of all current paths which define the state of each transistor gate. In order to obtain these paths, the circuit representation is converted from a transistor net-list to a cone net-list.

A cone is defined as being, for each circuit node connected to at least one transistor gate, the set of branches, which, from this node, attain a power supply or an external connector on the traversal of transistor source-drain junctions. Each branch consists of links corresponding to the transistors traversed. These branches therefore reveal the signals governing the state of the transistor gate(s) for which the cone is being constructed.

A set of cones is therefore obtained (completely defining the state of all transistor gates and drivable external connectors), each of which contain a set of branches.

This set of branches allows us to express the behaviour of the cone and hence generate a boolean expression for the state of the corresponding transistor gate. This expression is in fact composed of two parts: the function which represents the conditions necessary for Vdd to impose (Sup), and the equivalent for Vss (Sdn).

In reality these conditions have to be verified globally, this means that Sup and Sdn are expressed in terms of the logic surrounding the cone. The user defines the depth, in terms of logic gates, used for the expansion.

4. 2. 2. Timing Arcs

After circuit partitioning, each individual cone is characterized in terms of delay. First of all, a causality graph is obtained for each cone.

This cone causality graph is deduced directly from the structure of the cone. If an input drives a transistor in a branch to Vdd then the input generates an up transition on the output. If the transistor is NMOS then an up transition on the input creates the up on the output, so the timing arc is uu. A similar logic is applied for inputs driving PMOS transistors and for transistors in Vss branches. Up to four possible timing arcs can exist for each cone input.

Each timing arc can have a maximum and a minimum value. The aim is to obtain the maximum and minimum delays between all possible transitions of all cone inputs and the possible transitions of the output of the cone.

Each maximum and minimum timing arc is associated with a particular cone branch. This association is made by an initial calculation to obtain the most resistive (or least resistive for minimum) branch giving the timing arc transition.

The analysis of this branch provides the timing model (delay and slope) for the timing arc.

4. 2. 3. Current Characterization

A branch is made up of a number of transistors (PMOS and NMOS) connected in series. The characterization of the timing arc is made by an analysis of the current characteristics of each transistor in the branch. Two special cases, however, should be mentioned:

a) A cone may contain identical parallel branches. If the branch to characterize is part of a set of parallel branches then the current through all branches of the set is used to characterize the timing arc.

b) A transistor in a branch may be part of a transfer gate transistor pair. In this case the current characteristic is calculated using both NMOS and PMOS transistors of the transfer gate. HITAS assumes that both these transistors conduct simultaneously.

4. 2. 4. Algorithm Assumptions

The basic assumptions made by HITAS are:

a) A full swing (Vdd to Vss or Vss to Vdd) on the cone output occurs as a result of a full swing on a single cone input.

b) Separate cone inputs do not switch simultaneously.

c) For each branch characterization, only one transistor is considered to switch. Transfer gates and series connected transistors with coupled gates are handled as special cases.

These assumptions are necessary for the partitioning and characterization algorithm to provide a valid result. If these general assumptions hold for a particular circuit structure, then HITAS is applicable.

In the next section we present a selection of design structures for which these assumptions hold.

4. 3. HITAS Digital Structures

4. 3. 1. CMOS Gates

HITAS is applicable to all basic CMOS gates regardless of the implementation (invertors, buffers, NAND, NOR, etc). All kinds of exclusive or gates, including the implementation shown in the following figure, can be handled directly using HITAS. No special configuration is necessary.

4. 3. 2. Pass-Transistor and Transmission Gate Logic

HITAS is applicable to custom digital designs using pass-transistor or transmission gate logic. This often occurs in multiplexer implementations such as those shown in the following figure.

These structures are handled automatically by HITAS. However, care must sometimes be taken that the partitioning is performed correctly. HITAS may require information about the correlation between selector inputs if this correlation is not present in the block under analysis.

4. 3. 3. Clocked CMOS Logic

HITAS is applicable to high-speed custom techniques such as clocked CMOS logic. In particular HITAS is well suited to the analysis of Domino-Precharge based designs. Figure 6 shows a typical Domino precharge architecture handled by HITAS.

Each precharge stage is sometimes followed by a keeper or level hold structure. These pose no problem for HITAS.

For full handling of this kind of logic it is necessary to activate the automatic precharge detection for the partitioning phase as well as precharge verification during the static timing analysis phase.

4. 3. 4. Static Latches and Flip-Flops

HITAS incorporates, during the partitioning phase, an advanced algorithm to automatically detect any kind of fully static latch designed using an active feedback loop.

Both conflictual (e.g. inverter feedback) and non-conflictual (e.g. tristate feedback) latches are handled.

Latches can contain any number of clock inputs as well as asynchronous set and reset inputs. All these input types are identified automatically. Following figure shows a number of different latch types handled by HITAS.

Flip-flops are treated as two separate latches (master and slave). HITAS has an option to automatically detect flip-flops. This option can be used simply to report to the user the nodes recognised as the master nodes and the slave nodes. Alternatively, it is possible, for some flip-flops, to group the master and slave and perform a simplified flip-flop timing verification.

4. 3. 5. Dynamic Latches

HITAS can also be used to recognise dynamic latches such as the simple example shown in the following figure.

Recognition of dynamic latches is a configuration option of HITAS. Some care should be taken as there is can be ambiguity with a tristate bus.

HITAS uses the functional analysis of the partitioning phase to determine whether a node can be a dynamic latch. An internal node for which all drivers can be deactivated is considered to be a dynamic latch unless HITAS is told explicitly otherwise.

4. 4. HITAS Analog Structures

In this section we review a selection of typical analog structures which HITAS cannot handle directly.

4. 4. 1. Sense Amplifier

Following figure shows a typical sense amplifier building block. This structure, typically found in memories, senses a difference in potential between two inputs and provides an output of 1 or 0 depending which is the greater.

It should be quite clear from the HITAS assumptions that this structure cannot be handled. In effect it requires two input to switch simultaneously and neither of these inputs are full-swing.

4. 4. 2. Differential Amplifier

Following figure shows a typical long-tailed pair implementation of a differential amplifier. The operation is very similar to the sense amplifier. This is a basic analog amplifier building block but can also be found in high-speed digital logic styles such as CML.

Again the basic HITAS assumptions are not respected here since two inputs switch simultaneously even though they may be full-swing (for differential digital logic).

4. 4. 3. Voltage Generator

HITAS cannot calculate static power supply values produced by internal voltage generator circuits. The values of the voltages must be provided explicitly to HITAS using Vcard directives in the spice netlist.

For example, following figure shows a simple voltage divider circuit. This may occur in a netlist to provide a secondary lower power supply value to reduce power consumption. Here, the user is required to specify a Vcard at the output of this voltage divider to specify its effect.

4. 4. 4. Typical Analog Devices

HITAS is not directly applicable to common analog building blocks found in mixed-signal designs. These include: