5. Inverter

5. 1. Design Description

This example presents HITAS elementary concepts, based upon a simple inverter design and later an inverter chain.

The first example takes place in the inv/ directory.

5. 2. Database Generation

5. 2. 1. Principles

The database generation follows the steps below:

5. 2. 2. Global Configuration

The complete configuration required for the database generation takes place in the db.tcl. The script also launches the commands that effectively generate that database.

Configuration variables are set in the Tcl script by the mean of the avt_config function.

avt_config tasGenerateConeFile yes
tells the tool to dump on disk the .cns file, which contains the partitions (the cones) created by the partitioning algorithm.
avt_config avtVerboseConeFile yes
tells the tool to dump on disk the .cnv file, which is a more readable version.
avt_config simVthHigh 0.8
High threshold of the slope.
avt_config simVthLow 0.2
Low threshold of the slope.
avt_config simSlope 20e-12
Transient time of the slope in second.
avt_config simToolModel ngspice
tells the tool the technology file type (which simulator it is designed for)

The temperature and supplies specifications take place in the inv.spi file:

.TEMP 125
Vsupply vdd 0 DC 1.62
Vground vss 0 DC 0

5. 2. 3. Technology Integration

The technology file is included with a SPICE .INCLUDE directive in the inv.spi file (in the case of recursive inclusions, paths must be absolute).

In the present example, the .INCLUDE directive is used.

.INCLUDE ../techno/bsim4_dummy.ng

5. 2. 4. Database Generation

The generation launch is done through the command hitas:

avt_LoadFile inv.spi spice
set fig [hitas inv] 

The hitas function takes as argument the name of the figure (the subckt for a SPICE netlist) to analyze. The tas function returns a pointer on the timing database newly created. This pointer can be used as an input to further steps of verification, thus avoiding costly re-reading of the timing database from the disk.

To perform the database generation, just launch the script db.tcl

5. 3. Database Analysis

5. 3. 1. Database overview

At this step of the analysis process, the timing database of the adder sub-circuit consists of four files:

DTX file All the timing arcs of the sub-circuit, based upon the characterization of the "cones" created during the partitioning phase.
STM file The models that allow to computing the delay values for timing arcs and timing paths.
RCX file The interconnect elements (RC) at the physical boundary of the sub-circuit. This file is used for hierarchy purposes, allowing the partial flatten of interconnections at upper levels of hierarchy.

5. 3. 2. Database properties

The script db.tcl presents also Tcl access to the properties of the database:

Other properties are available. See HITAS Reference Guide.

6. Inverter Chain

6. 1. Design Description

This second example (also in directory inv/) presents HITAS database construction and database browsing concepts, based upon a inverter-chain design (file inv_chain.spi).

6. 2. Database properties

The script db_chain.tcl performs the database construction in the same way than the previous example. It also presents Tcl acces to the properties of the database:

Other properties are available. See HITAS Reference Guide.

6. 3. Path Reports

The script report.tcl shows a typical path report. The commands in the script are the following:

set fig [ttv_LoadSpecifiedTimingFigure inv_chain]

This command loads the timing database (.dtx, .stm and .cns files) into the program's memory.

set clist [ttv_GetPaths $fig * * rf 5 critic path max]

This command looks for the 5 longest paths (5 critic path max) in the circuit starting and ending on any terminal node (* *), with a rising transition on start node and a falling transition on the end node (rf). A terminal node is a pin or a latch.

set f [fopen inv_chain.paths "w+"]

This commands opens a file inv_chain.paths for further writing.

ttv_DisplayPathListDetail $f $clist

This command prints in file inv_chain.paths the result ($clist) of the previous command ttv_GetPaths. For results on standard output, replace $f by stdout. The output looks like:

 
     Voltage :        1.62V 
     Temperature :    125 degree C 
 
      *** Path list (unit:[ns]) *** 
 
 Path     Start     Start      Path     Total      Data    Ending       Start                  
           time     slope     delay     delay       lag     slope       From_node      To_node 
______________________________________________________________________________________________ 
    1     0.000     0.200     0.397     0.397     0.000     0.031   (R) in         (F) out     
 
Node type Index: 
   (C) : Clock node          (L) : Latch node         (F) : Flip-flop node 
   (B) : Breakpoint node     (K) : Latch command node (S) : Output connector node 
   (SZ): Output HZ connector (N) : Precharge node 
 
      *** Path details (unit:[ns]) *** 
 
Path (1) :  
 
        Delay                                                                        
      Acc    Delta    R/F     Cap[pf]   Type   Node_Name        Net_Name     Line    
   _________________________________________________________________________________ 
     0.000   0.000 0.200 R      0.020          in               in                   
     0.070   0.070 0.094 F      0.027          1                1             inv    
     0.186   0.116 0.111 R      0.027          2                2             inv    
     0.258   0.072 0.074 F      0.027          3                3             inv    
     0.372   0.114 0.106 R      0.027          4                4             inv    
     0.397   0.025 0.031 F      0.007    (S)   out              out           inv    
   _________________________________________________________________________________ 
     0.397   0.397            (total)                                                
 

There is actually only one path in this inverter chain.