13. Timing Characterization (.lib)

13. 1. Setup and Hold Constraints Formulas

Interface Setup and hold constraints are computed for each latch and register. They are computed with respect to the following formulas:

setup = data_path_max - clock_path_min
hold = clock_path_max - data_path_min

The following diagram gives an example of clock path and data path.

With such definitions of data and clock paths, the above formulas give optimistic values for setup and hold times. Therefore, a corrective factor is added to those values. The corrective factor for setup is called the "intrinsic setup of the latch"; the corrective factor for hold is called "intrinsic hold of the latch". The formulas now become:

setup = data_path_max - clock_path_min + intrinsic_setup
hold = clock_path_max - data_path_min + intrinsic_hold

13. 1. 1. Setup Correction

For setup time, the calculus is as follow:

The formula for setup becomes:

setup = data_path_max + t_loop - (clock_path_min + t2 - t1)

The corrective factor for setup is:

intrinsic_setup = t_loop - (t2 - t1)

13. 1. 2. Hold Correction

For hold time, the calculus is as follow:

The formula for hold becomes:

hold = clock_path_max + (t2 - t1) - data_path_min

The corrective factor for hold is:

intrinsic_hold = t2 - t1

13. 2. Performing the Characterization

The purpose of timing abstraction is to create a .lib file - containing setup, hold and access information of the design - from an already existing timing figure. Within the avt_shell Tcl interface, timing abstraction is performed with the function tmabs

BehFigure is a description of the functionality that can be associated with the design in the .lib file. For the moment it takes the NULL value.

TimingFigure is the database itself, the one the .lib file will be created from. Timing abstraction only uses the .dtx file. The database can be obtained by two ways. Through the hitas function, with the appropriate configuration allowing correct database construction:

avt_config ...
avt_config ...
 
set fig [hitas my_design]

If the timing database has already been constructed, the path view can be obtained from the .dtx file with the following command:

set fig [ttv_LoadSpecifiedTimingFigure my_design]

Timing abstraction requires additionnal information concerning clock definition (in order to construct correct setup/hold/access relationships). Clock definition and timing abstraction are then done as follow:

inf_SetFigureName my_design
create_clock -period 3000 ck
set abs_fig [tmabs $fig NULL * * *]

The -period value is irrelevant but is needed to respect SDC syntax. The .lib file is generated from the abstracted timing figure abs_fig as follow:

lib_DriveFile [list $abs_fig] NULL my_design.lib max

13. 3. Advanced Configuration

13. 3. 1. Input Slope and Output Load Axis

User-defined input slopes can be defined with the function inf_DefineSlopeRange. This function affects the way lookup-table axis are constructed. Be aware that inf_DefineSlopeRange should be applied before calling the hitas function:

inf_SetFigureName my_design
inf_DefineSlopeRange default {100e-12 150e-12 350e-12} custom
set fig [hitas my_design]

The same remarks apply to inf_DefineCapacitanceRange.

13. 3. 2. Capacitances in the .lib file

By default, capacitance values are given for input connectors only, as an average value. The given value is the equivalent capacitance allowing to compute the driving gate's delay at vdd/2. Capacitance ranges as well as different rise/fall capacitances can be obtained by tuning the elpCapaLevel variable (values 1 or 2).

Capacitances can also be given for output connectors (set tmaDriveCapaOut variable to yes). In such a case, the output delay is given WITHOUT taking into account the output connector's capacitance.

13. 4. Cell Library

Here is given an example Tcl script performing the timing abstraction of a list of standard cells, into a single .lib file:

avt_config tasBefig yes
avt_config tmaFunctionalityMode w
 
avt_LoadFile ./bsim3_018.tech spice
 
foreach cell { ao2o22 ff2 inv mux2 na2 } {
    avt_LoadFile $cell.spi spice
 
    set fig [hitas $cell]
    set beh_fig NULL
    set abs_fig [tma_abstract $fig $beh_fig]
 
    lappend fig_list $abs_fig
    lappend beh_list $beh_fig
}
 
lib_drivefile $fig_list $beh_list "stdcells.lib" max