Table of Contents
1. Input Files
2. Output Files
3. Log Files
4. Configuration Variables
5. Tcl Interface
6. Error Codes
Chapter 4 Subsections
4. Configuration Variables
4. 1. License Server
4. 2. Environment
4. 3. Log File and Error Policy
4. 4. Names
4. 5. Transistor Characterization
4. 6. Input Netlist and Parasitics
4. 7. SPICE Parser
4. 8. SPICE Driver
4. 9. VHDL Parser/Driver
4. 10. VERILOG Parser/Driver
4. 11. DSPF/SPEF Parser
4. 12. General Configuration
4. 13. Disassembly
4. 13. 1. Functional Analysis
4. 13. 2. Transistor Orientation
4. 13. 3. Latch Recognition
4. 13. 4. Pattern Matching
4. 13. 5. Cone Output Files
4. 14. Timing DB Construction
4. 14. 1. Special Elements
4. 14. 2. Output Files
4. 14. 3. Delay Models
4. 14. 4. Delays
4. 14. 5. RC Networks
4. 15. Path Browsing
4. 16. SDC Support
4. 17. Static Timing Analysis
4. 18. Statistical Analysis
4. 19. Crosstalk Analysis
4. 19. 1. Running
4. 19. 2. Models
4. 19. 3. Convergence
4. 19. 4. Reports
4. 19. 5. Scores
4. 20. Timing Abstraction
4. 20. 1. Input Files
4. 20. 2. Output Files
4. 20. 3. Units
4. 21. Pattern Matching
4. 22. Hierarchical Pattern Matching
4. 23. Simulator Linking
4. 23. 1. Simulation Tool Parameters
4. 23. 2. Extraction of the Simulation Results
4. 23. 3. Simulation Conditions Parameters
4. 23. 4. Simulation Transient Parameters
4. 23. 5. Simulation Thresholds Parameters
4. 23. 6. Simulation Input/Output Constraints Parameters
4. 24. API Specific
4. 25. SSTA Analysis