Re: [openrisc] OR1KSIM is it cycle accurate

["Damjan Lampret" <lampret@opencores.org>]

Mike,

there are some features that allow modelling of system for benchmark
purposes. To benchmark is not enough to model only the processor but also
memory latency etc (memory and memory controller etc). You can set what are
delays of accessing caches, MMUs delays, delay of memory controller and
memories etc. But this is only to about 95% accurate. For 100% you would
have to model instruction interdependency by implementing exact model of
implementation pipeline (for example or1200 pipeline would have to be
implemented). Right now there is a feature that will allow you to model the
pipeline from somewhat high level point of view - for example you can model
interdependcy of instructions to some level. For example a load instruction
followed by an add instruction, the simulator will delay execution of add
until load is completed. For architectual tradeofs you can also set how many
"execution units" you have, so effectively you could model a superscalar
processor, setting for example to have 2 load/store units, 3 ALU units etc.
The latter needs to be set in execute.c (I don't remember the exact file).

regards,
Damjan


----- Original Message ----- 
From: "Mike Wiles" <mwiles@austin.rr.com>
To: <openrisc@opencores.org>
Sent: Wednesday, August 20, 2003 3:04 PM
Subject: Re: [openrisc] OR1KSIM is it cycle accurate


> If you want to do benchmarks or architectural tradeoffs
> you need a cycle accurate simulator.
>
> Thanks, Mikew
>
> At 08:03 AM 08/20/2003 +0200, you wrote:
>
> >On Tuesday 19 August 2003 17:08, mwiles@austin.rr.com wrote:
> > > Hi,
> > > Can you tell me if the OR1KSIM is a cycle accurate simualtor?
> >No, but why would you need cycle accurate sim anyway?
> >
> >Marko
> >
> >
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