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[cvs-checkins] pci/rtl/verilog pci_bridge32.v top.v

To: cvs-checkins@opencores.org
Subject: [cvs-checkins] pci/rtl/verilog pci_bridge32.v top.v
From: OpenCores CVS Agent <cvs@www.opencores.org>
Date: Thu, 21 Aug 2003 22:49:32 +0200
Sender: owner-cvs-checkins@opencores.org

CVSROOT:	/home/oc/cvs
Module name:	pci
Changes by:	tadejm	03/08/21 22:49:30

Modified files:
	rtl/verilog    : pci_bridge32.v top.v 

Log message:
	Added signals for WB Master B3.

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