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[openrisc] Re: openrisc-digest V1 #441

To: openrisc@opencores.org
Subject: [openrisc] Re: openrisc-digest V1 #441
From: paul <paulw@mmail.ath.cx>
Date: Thu, 19 Jun 2003 01:27:25 -0700
References: <200306181655.h5IGtj4x008844@www.opencores.org>
Reply-To: openrisc@opencores.org
Sender: owner-openrisc@opencores.org
User-Agent: Mozilla/5.0 (X11; U; Linux i386; en-US; rv:1.0.2) Gecko/20030203

Hi

 From ISE manual, XCV 600 to XCV 800 require 512M of memory.
That might be your problem that it takes so long.

openrisc-digest wrote:

> openrisc@opencores.org	 openrisc-digest V1 #441
>
>
>----------------------------------------------------------------------
>From: hy kim <boina9456@hanafos.com>
>Date: Wed, 18 Jun 2003 15:35:15 +0900
>Subject: Re: [openrisc] How can i synthesize or1200?
>
>kevin@opencores.org wrote:
>
>  
>
>>hi,all
>>   i have got the source code from the cvs,and changed 
>>the "xsv_fpga_top.prj" in the "xess\xsv_fpga\orp_soc\syn\synplify" to let 
>>synplify find the files.but when i synthezised it ,synplify told me several 
>>files couldn't be found.then i copy those files from ".old".this time 
>>synplify runs well.but complie takes such a long time!i waited half an 
>>hour and stop it.my PC is P4 2.4 and 256MB memory.can anyone tell me 
>>if this is normal?
>>   
>>--
>>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>>
>> 
>>
>>    
>>
>I guess that sram memory are too much.
>
>Please comment a line "'define SDRAM_GENERIC" in rtl/mem_if/sram_top.v
>and retry.
>
>Regards.
>
>hy kim
>
>
>
>--
>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: "zhustudio" <zhustudio@ict.ac.cn>
>Date: Wed, 18 Jun 2003 18:9:11 +0800
>Subject: [openrisc] about mips of or1200
>
>hi,
>
>i have found that the mips of or1200 is to low.
>Assuming the ording instructions, the or1200's mips is 2 times slow to
>the system clock. (WISHBONE bus run 2_divide sys_clk)
>And with cache, the simulation tell me that it is only 8-10 times slow
>to system clock. 
>I have run the test under orp_soc/sw. so i think the buttleneck of it is the width of WISHBONE bus.
>dose anyone try to enchance the performance?
>
>Jiahui Zhu
>
>Email: zhustudio@ict.ac.cn
>Date: 2003-06-18
>
>
>
>--
>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: kevin@opencores.org
>Date: Wed, 18 Jun 2003 14:24:27 -0100
>Subject: Re: [openrisc] How can i synthesize or1200?
>
>24:30 2003
>Received: (from majordomo@localhost)
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>Date: Wed, 18 Jun 2003 14:24:27 -0100
>Message-Id: <200306181524.h5IFORUt031137@www.opencores.org>
>Subject: Re: [openrisc] How can i synthesize or1200?
>To: openrisc@opencores.org
>From: kevin@opencores.org
>Sender: owner-openrisc@opencores.org
>Precedence: bulk
>Reply-To: openrisc@opencores.org
>
>hi,
>     i can't find the "'define SDRAM_GENERIC" in any file in the 
>dictionary.when i comment the "'define SRAM_GENERIC" ,i get several 
>errors.so,what can i do?where can i get a complete , synthesizable 
>source code?
>
>----- Original Message ----- 
>From: hy kim <boina9456@h... > 
>To: openrisc@o...  
>Date: Wed, 18 Jun 2003 15:35:15 +0900 
>Subject: Re: [openrisc] How can i synthesize or1200? 
>
>  
>
>>kevin@o...  wrote: 
>>
>>    
>>
>>>hi,all 
>>>   i have got the source code from the cvs,and changed 
>>>the "xsv_fpga_top.prj" in the 
>>>      
>>>
>>"xess\xsv_fpga\orp_soc\syn\synplify" to let 
>>    
>>
>>>synplify find the files.but when i synthezised it ,synplify 
>>>      
>>>
>>told me several 
>>    
>>
>>>files couldn't be found.then i copy those files from 
>>>      
>>>
>>".old".this time 
>>    
>>
>>>synplify runs well.but complie takes such a long time!i waited 
>>>      
>>>
>>half an 
>>    
>>
>>>hour and stop it.my PC is P4 2.4 and 256MB memory.can anyone 
>>>      
>>>
>>tell me 
>>    
>>
>>>if this is normal? 
>>>
>>>
>>>
>>>
>>>
>>>      
>>>
>>I guess that sram memory are too much. 
>>
>>Please comment a line "'define SDRAM_GENERIC" in 
>>rtl/mem_if/sram_top.v 
>>and retry. 
>>
>>Regards. 
>>
>>hy kim 
>>
>>    
>>
>--
>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: kevin@opencores.org
>Date: Wed, 18 Jun 2003 14:25:17 -0100
>Subject: Re: [openrisc] How can i synthesize or1200?
>
>25:18 2003
>Received: (from majordomo@localhost)
>	by www.opencores.org (8.12.8/8.12.8) id h5IFPI85031248
>	for openrisc-list; Wed, 18 Jun 2003 14:25:18 -0100
>X-Authentication-Warning: localhost.localdomain: majordomo set sender to owner-openrisc@opencores.org using -f
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>	for openrisc@opencores.org; Wed, 18 Jun 2003 14:25:17 -0100
>Date: Wed, 18 Jun 2003 14:25:17 -0100
>Message-Id: <200306181525.h5IFPH0b031236@www.opencores.org>
>Subject: Re: [openrisc] How can i synthesize or1200?
>To: openrisc@opencores.org
>From: kevin@opencores.org
>Sender: owner-openrisc@opencores.org
>Precedence: bulk
>Reply-To: openrisc@opencores.org
>
>----- Original Message ----- 
>From: hy kim <boina9456@h... > 
>To: openrisc@o...  
>Date: Wed, 18 Jun 2003 15:35:15 +0900 
>Subject: Re: [openrisc] How can i synthesize or1200? 
>
>  
>
>>kevin@o...  wrote: 
>>
>>    
>>
>>>hi,all 
>>>   i have got the source code from the cvs,and changed 
>>>the "xsv_fpga_top.prj" in the 
>>>      
>>>
>>"xess\xsv_fpga\orp_soc\syn\synplify" to let 
>>    
>>
>>>synplify find the files.but when i synthezised it ,synplify 
>>>      
>>>
>>told me several 
>>    
>>
>>>files couldn't be found.then i copy those files from 
>>>      
>>>
>>".old".this time 
>>    
>>
>>>synplify runs well.but complie takes such a long time!i waited 
>>>      
>>>
>>half an 
>>    
>>
>>>hour and stop it.my PC is P4 2.4 and 256MB memory.can anyone 
>>>      
>>>
>>tell me 
>>    
>>
>>>if this is normal? 
>>>
>>>
>>>
>>>
>>>
>>>      
>>>
>>I guess that sram memory are too much. 
>>
>>Please comment a line "'define SDRAM_GENERIC" in 
>>rtl/mem_if/sram_top.v 
>>and retry. 
>>
>>Regards. 
>>
>>hy kim 
>>
>>    
>>
>--
>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>From: "Damjan Lampret" <lampret@opencores.org>
>Date: Wed, 18 Jun 2003 17:09:50 -0700
>Subject: Re: [openrisc] is there a way to rebuild or1ksim from verilog source
>
>No. You need to add your instruction in or1ksim manually.
>
>regards,
>Damjan
>
>----- Original Message -----
>From: "paul" <paulw@mmail.ath.cx>
>To: <openrisc@opencores.org>
>Sent: Wednesday, June 18, 2003 2:52 AM
>Subject: [openrisc] is there a way to rebuild or1ksim from verilog source
>
>
>  
>
>>Hi
>>
>>Is there a way to rebuild or1ksim from "or1200" *.v verilog source?
>>That is, can I add an instruction to or1200, and then rebuild the
>>or1ksim, to test the new instruction?
>>
>>If not, is there another way to test modification to or1200?
>>
>>Thanks.
>>
>>
>>--
>>To unsubscribe from openrisc mailing list please visit
>>    
>>
>http://www.opencores.org/mailinglists.shtml
>  
>
>
>--
>To unsubscribe from openrisc mailing list please visit http://www.opencores.org/mailinglists.shtml
>
>----------------------------------------------------------------------
>End of openrisc-digest V1 #441
>-
>To unsubscribe from openrisc-digest mailing list please visit http://www.opencores.org/mailinglists.shtml
>  
>



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