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Re: [openrisc] OR1200 ASIC Success probabilities.
Hi again. :)
> Christian,
>
> first I need to say that OR1200 has been intentionally split into many
> submodules for better overview. It does not mean that many modules mean
> slower design. You can put everything in a single module and it will be just
> as slow as many modules. However it is true to say if you would synthesize
> OR1200 submodule by submodule then results would not be good as inter module
> optimization might be less effective.
>
> It is important to point out that all the effort so far went mostly into
> making sure the core works properly and only limited effort went into speed
> optimizations. All speed optimizations are welcome (I'm thinking to create a
> branch that could be used by people to optimize it for speed).
> Looking at this path it looks strange indeed. The dbg module and sprs module
> up to genpc/spr_pc_we could be path of one path and the rest should be a
> different path. Second path starting in genpc_taken is part of insn fetch
> logic, instruction cache/immu abort logic. Because OR1200 has only 5 stage
> pipeline this path is a bit long due to a lot of different logic needed to
> perform all the necessary steps in insn fetch (and more important if insn is
> aborted, fetch stalled resulting in stall of pipeline etc etc).
Yes. We took a look at that. the spr_pc_we is only used for debug unit to
load pc with data via mtspr/mfspr? or is it used by any other logic?
Are there any programs that could use spr to load up the pc for any
practical purposes? Or have i got everything wrong?
> It is important to take into account speed of your RAMs. As in some cases it
> can happen that RAMs used for data/insn caches and for MMUs are so slow that
> in fact those paths starting at RAMs are timing critical and not this path
> that you brought up.
> So in this case I think it is possible to split this path and save 1ns.
>
> regards,
> Damjan
RAM will become an issue later. First we are looking at the madness going
on inside the cpu. :) If i cant get it to do 200MHz in 0.13 without
ramblocks.. how will it ever get better with them? I must produce a core
that is mean and lean before even adding RAMs. This is atleast how i look
at things. The paths though the rams are utterly predictable. ( since all
signals will pass the clock and a limit through the ramblock is defined ).
My biggest problem now is all the
combinatorical paths that are possibly valid, and possibly not.. I would
like to split those paths somehow.. Adding false paths to
the synthesis would only add on uglyness. And I really dont want to do
that. For example. After we did a temp hack on the spr_pc_we thingy.. i
hit another path.. take a look at this one please.
the short version:
in except/clk
out except/lr_sav
in genpc/binsn_addr
out genpc/icpu_adr_o
in immu/icpu_adr_i
out immu/icpu_err_o
in if/icpu_err_i
out if/if_stall
in freeze/if_stall
out freeze/ex_freeze
in except/ex_freeze
out except/flushpipe
in ctrl/flushpipe
out/rfwb_op
..
Now what i dont understand is how the current address passed to the immu
produces an err signal before it has even translated the address.
I do know that if the address is within the same page ( ie no page cross )
we really dont need to do another lookup. the tests for miss and fault
are for itlb_done and hit and protection bits. as any mmu would do it. :)
Problem is..
The lookup should be done completely in parallell instead? Or perhaps it
is and i can't see it. IC lookup should take 1 cyc, IMMU lookup 1 cyc
and then we should compare data since we use diffrent parts of the
address to IMMU and IC.
As I see it now: immu lookup is passed to ic fsm and then after 1 more
cycle it is compared to the tag in IC tag.
Could someone please explain how the mmu works in a bit more detailed
fashion? I seem to have confused myself trying to figure out
when data arrives.. :)
oh. and attached are a coulpe of pdf ( of tgif objs ) that we have
drawn in our project. they might be quite useless to you but i like to
have a graphical representation handy to look at. ( I havn't got
the insta-matrix-world-from-code-view down just yet. ;)
best regards
Christian M
or1200_if.pdf
or1200_except.pdf
or1200_freeze.pdf
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Pin | Edge | Net | Cell | Delay | Arrival | Time | Delay | Required | Slew | Fanout | Load | Pin | Wire |
| | | | | | Time | Given | Addition | Time | | | | Load | Load |
| | | | | | | To | | | | | | | |
| | | | | | | Start | | | | | | | |
| | | | | | | Point | | | | | | | |
|-----------------------------------------------+-------+-----------------------------------------------+-------------------------+-------+---------+-------+----------+----------+-------+--------+-------+-------+-------|
| clk_i | ^ | clk_i | | | 0.00 | | | -1.63 | 0.00 | 2099 | | 5.14 | |
| or1200_cpu/clk | ^ | or1200_cpu/clk | or1200_cpu | | 0.00 | | | -1.63 | | | | | |
| or1200_cpu/or1200_except/clk | ^ | or1200_cpu/or1200_except/clk | or1200_except | | 0.00 | | | -1.63 | | | | | |
| or1200_cpu/or1200_except/ex_pc_reg_17/Q | v | or1200_cpu/or1200_except/nbus_752N17N | HDDFFRPQ1 | 0.20 | 0.20 | | | -1.43 | 0.06 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_except/i_30716/Z | v | or1200_cpu/or1200_except/lr_sav[17] | HDBUFD4 | 0.11 | 0.31 | | | -1.32 | 0.04 | 4 | 0.02 | 0.01 | 0.01 |
| or1200_cpu/or1200_except/lr_sav[17] | v | or1200_cpu/lr_sav[15] | or1200_except | | 0.31 | | | -1.32 | | | | | |
| or1200_cpu/or1200_genpc/binsn_addr[17] | v | or1200_cpu/or1200_genpc/binsn_addr[17] | or1200_genpc | | 0.31 | | | -1.32 | | | | | |
| or1200_cpu/or1200_genpc/i_5143/binsn_addr[17] | v | or1200_cpu/or1200_genpc/i_5143/binsn_addr[17] | or1200_AWACL_ADD_UNS_30 | | 0.31 | | | -1.32 | | | | | |
| or1200_cpu/or1200_genpc/i_5143/i_15/Z | ^ | or1200_cpu/or1200_genpc/i_5143/n_285 | HDNOR2D1 | 0.10 | 0.41 | | | -1.21 | 0.12 | 1 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_165/Z | v | or1200_cpu/or1200_genpc/i_5143/n_435 | HDNOR2D2 | 0.05 | 0.46 | | | -1.17 | 0.05 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_2098/Z | v | or1200_cpu/or1200_genpc/i_5143/n_2278 | HDBUFD2 | 0.11 | 0.56 | | | -1.06 | 0.04 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_225/Z | ^ | or1200_cpu/or1200_genpc/i_5143/n_495 | HDNAN2D2 | 0.09 | 0.66 | | | -0.97 | 0.10 | 3 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_283/Z | v | or1200_cpu/or1200_genpc/i_5143/n_553 | HDNOR2D2 | 0.05 | 0.70 | | | -0.92 | 0.06 | 3 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_312/Z | ^ | or1200_cpu/or1200_genpc/i_5143/n_582 | HDAOI21DL | 0.20 | 0.90 | | | -0.72 | 0.23 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_370/Z | v | or1200_cpu/or1200_genpc/i_5143/n_640 | HDOAI21D1 | 0.05 | 0.95 | | | -0.67 | 0.07 | 1 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/i_400/Z | ^ | or1200_cpu/or1200_genpc/i_5143/O0[19] | HDEXOR2D1 | 0.14 | 1.09 | | | -0.53 | 0.08 | 3 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/i_5143/O0[19] | ^ | or1200_cpu/or1200_genpc/n_6993 | or1200_AWACL_ADD_UNS_30 | | 1.09 | | | -0.53 | | | | | |
| or1200_cpu/or1200_genpc/i_42/Z | ^ | or1200_cpu/or1200_genpc/pc_0N21N | HDMUX2D2 | 0.12 | 1.21 | | | -0.41 | 0.05 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_genpc/i_16972/I5[19] | ^ | or1200_cpu/or1200_genpc/i_16972/I5[19] | or1200_AWMUX_16_30 | | 1.21 | | | -0.41 | | | | | |
| or1200_cpu/or1200_genpc/i_16972/i_175/Z | v | or1200_cpu/or1200_genpc/i_16972/n_689 | HDMUXB4D1 | 0.24 | 1.45 | | | -0.17 | 0.04 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_genpc/i_16972/i_206/Z | ^ | or1200_cpu/or1200_genpc/i_16972/n_720 | HDMUXB2DL | 0.17 | 1.62 | | | -0.00 | 0.18 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_genpc/i_16972/i_454/Z | ^ | or1200_cpu/or1200_genpc/i_16972/O0[19] | HDNOR2M1D2 | 0.16 | 1.79 | | | 0.16 | 0.07 | 2 | 0.01 | 0.00 | 0.00 |
| or1200_cpu/or1200_genpc/i_16972/O0[19] | ^ | or1200_cpu/or1200_genpc/pc_1[21] | or1200_AWMUX_16_30 | | 1.79 | | | 0.16 | | | | | |
| or1200_cpu/or1200_genpc/i_150/Z | ^ | or1200_cpu/or1200_genpc/icpu_adr_o[21] | HDOA21M10D2 | 0.12 | 1.90 | | | 0.28 | 0.07 | 3 | 0.02 | 0.01 | 0.00 |
| or1200_cpu/or1200_genpc/icpu_adr_o[21] | ^ | or1200_cpu/icpu_adr_o[21] | or1200_genpc | | 1.90 | | | 0.28 | | | | | |
| or1200_cpu/icpu_adr_o[21] | ^ | icpu_adr_cpu[21] | or1200_cpu | | 1.90 | | | 0.28 | | | | | |
| or1200_immu_top/icpu_adr_i[21] | ^ | or1200_immu_top/icpu_adr_i[21] | or1200_immu_top | | 1.90 | | | 0.28 | | | | | |
| or1200_immu_top/i_51/Z | v | or1200_immu_top/n_11 | HDEXOR2D1 | 0.15 | 2.06 | | | 0.43 | 0.05 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_immu_top/i_37/Z | v | or1200_immu_top/n_2 | HDOR2D1 | 0.11 | 2.17 | | | 0.54 | 0.04 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_immu_top/i_94/Z | ^ | or1200_immu_top/n_244 | HDNOR3M1D2 | 0.07 | 2.24 | | | 0.62 | 0.09 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_immu_top/i_55/Z | v | or1200_immu_top/n_250 | HDNAN4D1 | 0.06 | 2.30 | | | 0.67 | 0.06 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_immu_top/i_61/Z | v | or1200_immu_top/n_52 | HDNAN3M1D2 | 0.14 | 2.44 | | | 0.82 | 0.05 | 1 | 0.01 | 0.01 | 0.00 |
| or1200_immu_top/i_62/Z | ^ | or1200_immu_top/icpu_err_o | HDNAN2M1D2 | 0.08 | 2.53 | | | 0.90 | 0.10 | 3 | 0.01 | 0.01 | 0.00 |
| or1200_immu_top/icpu_err_o | ^ | icpu_err_immu | or1200_immu_top | | 2.53 | | | 0.90 | | | | | |
| or1200_cpu/icpu_err_i | ^ | or1200_cpu/icpu_err_i | or1200_cpu | | 2.53 | | | 0.90 | | | | | |
| or1200_cpu/or1200_if/icpu_err_i | ^ | or1200_cpu/or1200_if/icpu_err_i | or1200_if | | 2.53 | | | 0.90 | | | | | |
| or1200_cpu/or1200_if/i_2/Z | v | or1200_cpu/or1200_if/if_stall | HDNOR2D2 | 0.05 | 2.57 | | | 0.95 | 0.06 | 3 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_if/if_stall | v | or1200_cpu/if_stall | or1200_if | | 2.57 | | | 0.95 | | | | | |
| or1200_cpu/or1200_freeze/if_stall | v | or1200_cpu/or1200_freeze/if_stall | or1200_freeze | | 2.57 | | | 0.95 | | | | | |
| or1200_cpu/or1200_freeze/i_24/Z | v | or1200_cpu/or1200_freeze/ex_freeze | HDOAI21M20D2 | 0.14 | 2.71 | | | 1.08 | 0.10 | 5 | 0.02 | 0.01 | 0.01 |
| or1200_cpu/or1200_freeze/ex_freeze | v | or1200_cpu/n_739 | or1200_freeze | | 2.71 | | | 1.08 | | | | | |
| or1200_cpu/or1200_except/ex_freeze | v | or1200_cpu/or1200_except/ex_freeze | or1200_except | | 2.71 | | | 1.08 | | | | | |
| or1200_cpu/or1200_except/i_77/Z | ^ | or1200_cpu/or1200_except/n_7 | HDAOI21D1 | 0.13 | 2.84 | | | 1.21 | 0.18 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_except/i_4/Z | v | or1200_cpu/or1200_except/n_26 | HDINVBD2 | 0.04 | 2.87 | | | 1.25 | 0.05 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_except/i_89/Z | ^ | or1200_cpu/or1200_except/n_2 | HDNAN2D1 | 0.07 | 2.94 | | | 1.31 | 0.09 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_except/i_9222/Z | v | or1200_cpu/or1200_except/n_505 | HDAOI211D1 | 0.06 | 3.00 | | | 1.37 | 0.08 | 1 | 0.01 | 0.00 | 0.00 |
| or1200_cpu/or1200_except/i_86/Z | ^ | or1200_cpu/or1200_except/flushpipe | HDINVD2 | 0.11 | 3.11 | | | 1.49 | 0.12 | 5 | 0.02 | 0.01 | 0.01 |
| or1200_cpu/or1200_except/flushpipe | ^ | or1200_cpu/flushpipe | or1200_except | | 3.11 | | | 1.49 | | | | | |
| or1200_cpu/or1200_ctrl/flushpipe | ^ | or1200_cpu/or1200_ctrl/flushpipe | or1200_ctrl | | 3.11 | | | 1.49 | | | | | |
| or1200_cpu/or1200_ctrl/i_147/Z | v | or1200_cpu/or1200_ctrl/n_244351 | HDNOR2D2 | 0.06 | 3.17 | | | 1.55 | 0.06 | 4 | 0.02 | 0.01 | 0.00 |
| or1200_cpu/or1200_ctrl/i_240/Z | v | or1200_cpu/or1200_ctrl/n_702 | HDBUFD4 | 0.12 | 3.29 | | | 1.67 | 0.05 | 7 | 0.03 | 0.02 | 0.01 |
| or1200_cpu/or1200_ctrl/i_251/Z | ^ | or1200_cpu/or1200_ctrl/n_25 | HDNAN2D2 | 0.07 | 3.36 | | | 1.74 | 0.07 | 1 | 0.01 | 0.00 | 0.00 |
| or1200_cpu/or1200_ctrl/i_144/Z | v | or1200_cpu/or1200_ctrl/n_22 | HDINVD2 | 0.04 | 3.40 | | | 1.77 | 0.04 | 2 | 0.01 | 0.01 | 0.00 |
| or1200_cpu/or1200_ctrl/i_193/Z | ^ | or1200_cpu/or1200_ctrl/n_615 | HDNAN2D2 | 0.04 | 3.44 | | | 1.82 | 0.05 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_ctrl/i_275/Z | ^ | or1200_cpu/or1200_ctrl/n_623 | HDNOR2M1D2 | 0.12 | 3.56 | | | 1.93 | 0.06 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_ctrl/i_78/Z | v | or1200_cpu/or1200_ctrl/n_350 | HDNAN4D1 | 0.06 | 3.61 | | | 1.99 | 0.07 | 1 | 0.00 | 0.00 | 0.00 |
| or1200_cpu/or1200_ctrl/rfwb_op_reg_1/D | v | | HDDFERPQ4 | 0.00 | 3.61 | | | 1.99 | 0.07 | | | | |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Path 2: VIOLATED Setup Check with Pin or1200_cpu/or1200_ctrl/rfwb_op_reg_1/CK
in except/clk
out except/lr_sav
in genpc/binsn_addr
out genpc/icpu_adr_o
in immu/icpu_adr_i
out immu/icpu_err_o
in if/icpu_err_i
out if/if_stall
in freeze/if_stall
out freeze/ex_freeze
in except/ex_freeze
out except/flushpipe
in ctrl/flushpipe
out/rfwb_op
or1200_genpc.pdf
or1200_immu_top.pdf
or1200_immu_tlb.pdf
or1200_ctrl.pdf