[openrisc] Hello. A couple questions

[Gavin Hurlbut <gjhurlbu@beirdo.ott.uplink.on.ca>]

Hello all.  I am a firmware designer with an Electrical Engineering background,
and I have been tinkering with the idea of making a multiprocessor computer
in my "spare" time for a few years now.  I just recently stumbled across the
OpenRISC project, and I am quite interested in its progress...  I have a few
questions:

1)  Is the CVS repository currently the only source of VHDL code for the OR1k?
    It seems to be a bit old, assuming work has been done on it in the last
    little while.

2)  Has anyone successfully synthesized the OR1k for a Xilinx Spartan-II?  If
    so, how many gates, etc does a core take, and how fast could you run it
    at?  Even simulation results would be cool.

3)  Has anyone started putting a L2-cache interface onto this core?  If I were
    to use it in a multiprocessor situation, L2-cache would be a necessity.

4)  Has anyone attempted using this core in a multiprocessor project?

I'm sure I'll think of a few more questions eventually :)

Thanks for your attention and help.

Ciao
Gavin