Re: [openrisc] cache control

["Damjan Lampret" <lampret@opencores.org>]

----- Original Message -----
From: <jimmy87@sunplus.com.tw>
To: <lampret@opencores.org>; <johan.rydberg@netinsight.se>;
<openrisc@opencores.org>
Sent: Tuesday, June 06, 2000 11:08 AM
Subject: [openrisc] cache control


>
>
> Hi Damjan,
> I don't know what I think is the same as yours about cache and MMU.
>
> 1. at reset, all addresses including insn and data are located
>      in uncached region.

Caches and MMU are disabled at reset so entire memory address space is not
cached.

> 2. Which one of cache and MMU should be enabled first?

Hmm, I think order is not so important. Not sure though...

> 3. Is there a permanent region which is always uncached?

Depends what you set with MMU. Everything is very custom. Including support
for cache coherency in SMP systems.

regards,
Damjan