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Re: [oc] to Andras

On Sat, Jul 06, 2002 at 09:30:50AM -0700, jae lim wrote:
> Hello Andras
> 
> My target technology is ASIC and I am using Ncverilog
> from cadence for the functional simulation.
> 
> Do you by any chance know if Ncverilog has the
> described capability?
> 
> Thanks a lot.

the asic vendor will supply a library describing their  gates 
as verilog primitives.  just read the vendor library into ncverilog 
together with your gate level netlist and preferably the 
sdf_annotation file. 
john
  
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