head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2003.11.20.05.07.57;	author tantos;	state Exp;
branches;
next	1.2;

1.2
date	2001.04.27.14.26.59;	author tantos;	state Exp;
branches;
next	1.1;

1.1
date	2001.04.25.15.05.30;	author tantos;	state Exp;
branches;
next	;


desc
@@


1.3
log
@Large update to new version of wb_tk. Major changes:
- Xilinx support added
- Altera support is poor: though it's there I haven't tested or even compiled it for quite some time
- Behavioral models are added
- Async master is completely new: it's much more complicated but actually works
- Cores are tested in real HW (x2s300e)
- wb_out_reg currently lacks byte-select support
- wb_in_reg is added as a trivial input register
@
text
@--
--  Wishbone bus tester utilities.
--
--  (c) Copyright Andras Tantos <andras_tantos@@yahoo.com> 2001/04/17
--  This code is distributed under the terms and conditions of the GNU General Public Lince.
--
--
-- ELEMENTS:
--    procedure wr_chk_val: writes a value, reads it back an checks if it's the same
--    procedure wr_val: writes a value
--    procedure rd_val: reads a value
--    procedure chk_val: checks (after read) a value

library IEEE;
use IEEE.std_logic_1164.all;

library wb_tk;
use wb_tk.technology.all;

package wb_test is
	procedure wr_chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	);
	procedure wr_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	);
	procedure rd_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		variable data: out STD_LOGIC_VECTOR
	);
	procedure chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	);


	procedure wr_chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	);
	procedure wr_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	);
	procedure rd_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		variable data: out STD_LOGIC_VECTOR
	);
	procedure chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	);
end wb_test;


package body wb_test is
	procedure wr_chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
		variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
	begin
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		stb_i <= '0';
		we_i <= '0';
		cyc_i <= '0';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		adr_i <= addr;
		dat_i <= data;
		cyc_i <= '1';
		stb_i <= '1';
		we_i <= '1';
		wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		cyc_i <= '0';
		stb_i <= '0';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1';
		adr_i <= addr;
		dat_i <= dat_undef;
		cyc_i <= '1';
		stb_i <= '1';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
		assert dat_o = data report "Value does not match!" severity ERROR;
		adr_i <= adr_zero;
		stb_i <= '0';
		cyc_i <= '0';
	end;

	procedure wr_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
		variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
	begin
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		stb_i <= '0';
		we_i <= '0';
		cyc_i <= '0';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		adr_i <= addr;
		dat_i <= data;
		cyc_i <= '1';
		stb_i <= '1';
		we_i <= '1';
		wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		cyc_i <= '0';
		stb_i <= '0';
		we_i <= '0';
	end;

	procedure rd_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		variable data: out STD_LOGIC_VECTOR
	) is
		variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
		variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
	begin
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		cyc_i <= '0';
		stb_i <= '0';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		adr_i <= addr;
		dat_i <= dat_undef;
		cyc_i <= '1';
		stb_i <= '1';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
		data := dat_o;
		adr_i <= adr_zero;
		stb_i <= '0';
		cyc_i <= '0';
	end;

	procedure chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in STD_LOGIC_VECTOR;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
		variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
	begin
		adr_i <= adr_zero;
		dat_i <= dat_undef;
		cyc_i <= '0';
		stb_i <= '0';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		wait until clk_i'EVENT and clk_i = '1';
		adr_i <= addr;
		dat_i <= dat_undef;
		cyc_i <= '1';
		stb_i <= '1';
		we_i <= '0';
		wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
		assert dat_o = data report "Value does not match!" severity ERROR;
		adr_i <= adr_zero;
		stb_i <= '0';
		cyc_i <= '0';
	end;

	procedure wr_chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable sadr: std_logic_vector(adr_i'RANGE);
	begin
		sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
		wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end;
	procedure wr_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable sadr: std_logic_vector(adr_i'RANGE);
	begin
		sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
		wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end;
	procedure rd_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		variable data: out STD_LOGIC_VECTOR
	) is
		variable sadr: std_logic_vector(adr_i'RANGE);
	begin
		sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
		rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end;
	procedure chk_val(
		signal clk_i: in STD_LOGIC;
		signal adr_i: out STD_LOGIC_VECTOR;
		signal dat_o: in STD_LOGIC_VECTOR;
		signal dat_i: out STD_LOGIC_VECTOR;
		signal we_i: out STD_LOGIC;
		signal cyc_i: out std_logic;
		signal stb_i: out STD_LOGIC;
		signal ack_o: in STD_LOGIC;
		constant addr: in integer;
		constant data: in STD_LOGIC_VECTOR
	) is
		variable sadr: std_logic_vector(adr_i'RANGE);
	begin
		sadr := to_std_logic_vector(addr,adr_i'HIGH+1);
		chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end;

end wb_test;

@


1.2
log
@Minor changes
@
text
@d16 3
a18 2
library synopsys;
use synopsys.std_logic_arith.all;
d123 153
a275 153
    procedure wr_chk_val(
    	signal clk_i: in STD_LOGIC;
    	signal adr_i: out STD_LOGIC_VECTOR;
    	signal dat_o: in STD_LOGIC_VECTOR;
    	signal dat_i: out STD_LOGIC_VECTOR;
    	signal we_i: out STD_LOGIC;
    	signal cyc_i: out std_logic;
    	signal stb_i: out STD_LOGIC;
    	signal ack_o: in STD_LOGIC;
    	constant addr: in STD_LOGIC_VECTOR;
    	constant data: in STD_LOGIC_VECTOR
    ) is
    	variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
    	variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	stb_i <= '0';
    	we_i <= '0';
    	cyc_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	adr_i <= addr;
    	dat_i <= data;
    	cyc_i <= '1';
    	stb_i <= '1';
    	we_i <= '1';
    	wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	cyc_i <= '0';
    	stb_i <= '0';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1';
    	adr_i <= addr;
    	dat_i <= dat_undef;
    	cyc_i <= '1';
    	stb_i <= '1';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
    	assert dat_o = data report "Value does not match!" severity ERROR;
    	adr_i <= adr_zero;
    	stb_i <= '0';
    	cyc_i <= '0';
    end procedure;

    procedure wr_val(
    	signal clk_i: in STD_LOGIC;
    	signal adr_i: out STD_LOGIC_VECTOR;
    	signal dat_o: in STD_LOGIC_VECTOR;
    	signal dat_i: out STD_LOGIC_VECTOR;
    	signal we_i: out STD_LOGIC;
    	signal cyc_i: out std_logic;
    	signal stb_i: out STD_LOGIC;
    	signal ack_o: in STD_LOGIC;
    	constant addr: in STD_LOGIC_VECTOR;
    	constant data: in STD_LOGIC_VECTOR
    ) is
    	variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
    	variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	stb_i <= '0';
    	we_i <= '0';
    	cyc_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	adr_i <= addr;
    	dat_i <= data;
    	cyc_i <= '1';
    	stb_i <= '1';
    	we_i <= '1';
    	wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	cyc_i <= '0';
    	stb_i <= '0';
    	we_i <= '0';
    end procedure;
    
    procedure rd_val(
    	signal clk_i: in STD_LOGIC;
    	signal adr_i: out STD_LOGIC_VECTOR;
    	signal dat_o: in STD_LOGIC_VECTOR;
    	signal dat_i: out STD_LOGIC_VECTOR;
    	signal we_i: out STD_LOGIC;
    	signal cyc_i: out std_logic;
    	signal stb_i: out STD_LOGIC;
    	signal ack_o: in STD_LOGIC;
    	constant addr: in STD_LOGIC_VECTOR;
    	variable data: out STD_LOGIC_VECTOR
    ) is
    	variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
    	variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	cyc_i <= '0';
    	stb_i <= '0';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	adr_i <= addr;
    	dat_i <= dat_undef;
    	cyc_i <= '1';
    	stb_i <= '1';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
    	data := dat_o;
    	adr_i <= adr_zero;
    	stb_i <= '0';
    	cyc_i <= '0';
    end procedure;
    
    procedure chk_val(
    	signal clk_i: in STD_LOGIC;
    	signal adr_i: out STD_LOGIC_VECTOR;
    	signal dat_o: in STD_LOGIC_VECTOR;
    	signal dat_i: out STD_LOGIC_VECTOR;
    	signal we_i: out STD_LOGIC;
    	signal cyc_i: out std_logic;
    	signal stb_i: out STD_LOGIC;
    	signal ack_o: in STD_LOGIC;
    	constant addr: in STD_LOGIC_VECTOR;
    	constant data: in STD_LOGIC_VECTOR
    ) is
    	variable adr_zero: STD_LOGIC_VECTOR(adr_i'RANGE) := (others => '0');
    	variable dat_undef: STD_LOGIC_VECTOR(dat_i'RANGE) := (others => 'U');
    begin
    	adr_i <= adr_zero;
    	dat_i <= dat_undef;
    	cyc_i <= '0';
    	stb_i <= '0';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	wait until clk_i'EVENT and clk_i = '1';
    	adr_i <= addr;
    	dat_i <= dat_undef;
    	cyc_i <= '1';
    	stb_i <= '1';
    	we_i <= '0';
    	wait until clk_i'EVENT and clk_i = '1' and ack_o = '1';
    	assert dat_o = data report "Value does not match!" severity ERROR;
    	adr_i <= adr_zero;
    	stb_i <= '0';
    	cyc_i <= '0';
    end procedure;
    
d288 1
a288 1
	    variable sadr: std_logic_vector(adr_i'RANGE);
d290 3
a292 3
	    sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
	    wr_chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end procedure;
d305 1
a305 1
	    variable sadr: std_logic_vector(adr_i'RANGE);
d307 3
a309 3
	    sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
	    wr_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end procedure;
d322 1
a322 1
	    variable sadr: std_logic_vector(adr_i'RANGE);
d324 3
a326 3
	    sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
	    rd_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end procedure;
d339 1
a339 1
	    variable sadr: std_logic_vector(adr_i'RANGE);
d341 5
a345 5
	    sadr := CONV_STD_LOGIC_VECTOR(addr,adr_i'HIGH+1);
	    chk_val(clk_i,adr_i,dat_o,dat_i,we_i,cyc_i,stb_i,ack_o,sadr,data);
	end procedure;
    
end package body wb_test;
@


1.1
log
@Major reorganization and some new elements added.
@
text
@d16 2
d68 50
d274 72
a345 1
end package body wb_test;@