head	1.5;
access;
symbols;
locks; strict;
comment	@# @;


1.5
date	2002.02.01.01.58.16;	author rudi;	state Exp;
branches;
next	1.4;

1.4
date	2001.09.07.15.34.38;	author rudi;	state Exp;
branches;
next	1.3;

1.3
date	2001.08.15.05.40.30;	author rudi;	state Exp;
branches;
next	1.2;

1.2
date	2001.08.07.08.00.44;	author rudi;	state Exp;
branches;
next	1.1;

1.1
date	2001.07.29.08.57.02;	author rudi;	state Exp;
branches;
next	;


desc
@@


1.5
log
@
- Updated make rules ...
@
text
@
all:	sim
SHELL = /bin/sh
MS=-s

##########################################################################
#
# DUT Sources
#
##########################################################################
DUT_SRC_DIR=../../../rtl/verilog
_TARGETS_=	$(DUT_SRC_DIR)/wb_dma_ch_pri_enc.v	\
		$(DUT_SRC_DIR)/wb_dma_ch_arb.v		\
		$(DUT_SRC_DIR)/wb_dma_pri_enc_sub.v	\
		$(DUT_SRC_DIR)/wb_dma_ch_sel.v		\
		$(DUT_SRC_DIR)/wb_dma_top.v		\
		$(DUT_SRC_DIR)/wb_dma_ch_rf.v		\
		$(DUT_SRC_DIR)/wb_dma_rf.v		\
		$(DUT_SRC_DIR)/wb_dma_wb_if.v		\
		$(DUT_SRC_DIR)/wb_dma_wb_mast.v		\
		$(DUT_SRC_DIR)/wb_dma_wb_slv.v		\
		$(DUT_SRC_DIR)/wb_dma_de.v		\
		$(DUT_SRC_DIR)/wb_dma_inc30r.v

##########################################################################
#
# Test Bench Sources
#
##########################################################################
_TOP_=test
TB_SRC_DIR=../../../bench/verilog
_TB_=		$(TB_SRC_DIR)/test_bench_top.v		\
		$(TB_SRC_DIR)/wb_slv_model.v		\
		$(TB_SRC_DIR)/wb_mast_model.v

##########################################################################
#
# Misc Variables
#
##########################################################################

#INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
#LOGF=-LOGFILE .nclog
#NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT

INCDIR=+incdir+./$(DUT_SRC_DIR)/ +incdir+./$(TB_SRC_DIR)/
LOGF=-l .nclog

UMC_LIB=/tools/dc_libraries/virtual_silicon/umc_lib.v
GATE_NETLIST = ../../../syn/out/wb_dma_top_ps.v

##########################################################################
#
# Make Targets
#
##########################################################################

ss:
	signalscan -do waves/waves.do -waves waves/waves.trn &

simxl:
	verilog +incdir+$(DUT_SRC_DIR) +incdir+$(TB_SRC_DIR)	\
	$(_TARGETS_) $(_TB_)

simw:
	@@$(MAKE) -s sim ACCESS="+access+r " WAVES="+define+WAVES"

sim:
	ncverilog -q +define+RUDIS_TB $(_TARGETS_) $(_TB_)      \
                $(INCDIR) $(WAVES) $(ACCESS) $(LOGF) +ncstatus  \
                +ncuid+`hostname`

gatew:
	@@$(MAKE) -s gate ACCESS="+access+r" WAVES="+define+WAVES"

gate:
	ncverilog -q +define+RUDIS_TB $(_TB_) $(UMC_LIB)        \
		$(GATE_NETLIST) $(INCDIR) $(WAVES) $(ACCESS)    \
		$(LOGF) +ncstatus +ncuid+`hostname`

hal:
	@@echo ""
	@@echo "----- Running HAL ... ----------"
	@@hal	-NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK	\
		+incdir+$(DUT_SRC_DIR) $(_TARGETS_)
	@@echo "----- DONE ... ----------"

clean:
	rm -rf	./waves/*.dsn ./waves/*.trn			\
		ncwork/inc* ncwork/.inc* ncverilog.key		\
		./verilog.* .nclog hal.log INCA_libs

##########################################################################
@


1.4
log
@
Changed reset to active high.
@
text
@a2 1

d42 7
a48 3
INCDIR="-INCDIR ./$(DUT_SRC_DIR)/ -INCDIR ./$(TB_SRC_DIR)/"
LOGF=-LOGFILE .nclog
NCCOMMON=-CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var -NOCOPYRIGHT
d66 1
a66 1
	@@$(MAKE) $(MS) sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"
d69 3
a71 15
	@@echo ""
	@@echo "----- Running NCVLOG ... ----------"
	@@$(MAKE) $(MS) vlog				\
		TARGETS="$(_TARGETS_)"			\
		TB="$(_TB_)"				\
		INCDIR=$(INCDIR)			\
		WAVES="$(WAVES)"
	@@echo ""
	@@echo "----- Running NCELAB ... ----------"
	@@$(MAKE) $(MS) elab				\
		ACCESS="$(ACCESS)" TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCSIM ... ----------"
	@@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
	@@echo ""
d74 1
a74 1
	@@$(MAKE) -s gate ACCESS="-ACCESS +r " WAVES="-DEFINE WAVES"
d77 3
a79 15
	@@echo ""
	@@echo "----- Running NCVLOG ... ----------"
	@@$(MAKE) $(MS) vlog				\
		TARGETS="$(UMC_LIB) $(GATE_NETLIST)"	\
		TB="$(_TB_)"				\
		INCDIR=$(INCDIR)			\
		WAVES="$(WAVES)"
	@@echo ""
	@@echo "----- Running NCELAB ... ----------"
	@@$(MAKE) $(MS) elab				\
		ACCESS="$(ACCESS)" TOP=$(_TOP_)
	@@echo ""
	@@echo "----- Running NCSIM ... ----------"
	@@$(MAKE) $(MS) ncsim TOP=$(_TOP_)
	@@echo ""
d89 3
a91 15
	rm -rf	./waves/*.dsn ./waves/*.trn		\
		ncwork/inc* ncwork/.inc* 		\
		./verilog.* .nclog hal.log

##########################################################################
#
# NCVLOG
#
##########################################################################

vhdl:
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK count -V93 hdl/counter.vhd
	ncvhdl $(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-WORK work -V93 $(TARGETS)
a92 8
vlog:
	ncvlog $(NCCOMMON) $(LOGF) 				\
		-WORK work $(WAVES) $(TB) $(TARGETS) $(INCDIR)

##########################################################################
#
# NCELAB
#
a93 17

elab:
	ncelab	$(NCCOMMON) $(LOGF) -APPEND_LOG 		\
		-WORK work $(ACCESS) -NOTIMINGCHECKS		\
		work.$(TOP)

##########################################################################
#
# NCSIM
#
##########################################################################

ncsim:
	ncsim	$(NCCOMMON) $(LOGF) -APPEND_LOG			\
		-EXIT -ERRORMAX 10 work.$(TOP)


@


1.3
log
@
- Changed IO names to be more clear.
- Uniquifyed define names to be core specific.
- Added Section 3.10, describing DMA restart.
@
text
@d46 2
d70 20
@


1.2
log
@

Split up priority encoder modules to separate files
@
text
@d5 1
a5 1
MS="-s"
d61 1
a61 1
	@@$(MAKE) -s sim ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"
d66 1
a66 1
	$(MAKE) $(MS) vlog				\
d73 1
a73 1
	$(MAKE) $(MS) elab				\
d77 1
a77 1
	$(MAKE) $(MS) ncsim TOP=$(_TOP_)
@


1.1
log
@

1) Changed Directory Structure
2) Added restart signal (REST)
@
text
@d2 2
d5 41
a45 1
#.QUIET
d47 8
a54 36
DMA_TARGETS=	../../../rtl/verilog/wb_dma_ch_arb.v		\
		../../../rtl/verilog/wb_dma_ch_pri_enc.v	\
		../../../rtl/verilog/wb_dma_ch_sel.v		\
		../../../rtl/verilog/wb_dma_top.v		\
		../../../rtl/verilog/wb_dma_ch_rf.v		\
		../../../rtl/verilog/wb_dma_rf.v		\
		../../../rtl/verilog/wb_dma_wb_if.v		\
		../../../rtl/verilog/wb_dma_wb_mast.v		\
		../../../rtl/verilog/wb_dma_wb_slv.v		\
		../../../rtl/verilog/wb_dma_de.v		\
		../../../rtl/verilog/wb_dma_inc30r.v		\


DMA_TB=		../../../bench/verilog/test_bench_top.v		\
		../../../bench/verilog/wb_slv_model.v		\
		../../../bench/verilog/wb_mast_model.v		\


TOP=test
INCDIR="-INCDIR ../../../rtl/verilog/ -INCDIR ../../../bench/verilog/"
#ACCESS="-ACCESS +r"
#WAVES=-DEFINE WAVES

dmawxl:
	verilog +incdir+verilog/ $(DMA_TARGETS) $(DMA_TB)

dmaw:
	@@$(MAKE) -s dma ACCESS="-ACCESS +r" WAVES="-DEFINE WAVES"

dmass:
	signalscan -do waves/dma.do -waves waves/waves.trn &

dma:
	@@$(MAKE) -s vlog TARGETS="$(DMA_TARGETS) $(DMA_TB)" INCDIR=$(INCDIR) WAVES="$(WAVES)" TOP=test
	@@$(MAKE) -s elab ACCESS="$(ACCESS)" TOP=test
	@@$(MAKE) -s sim  TOP=test
d56 6
a61 2
clean:
	rm -f .nclog ./waves/*.dsn ./waves/*.trn ./ncwork/inca.linux.* ./ncwork/.inc*
d63 16
a78 2
simx:
	ncverilog +incdir+verilog +incdir+test_bench $(DMA_TARGETS) $(DMA_TB)
d81 5
a85 1
	hal +incdir+./verilog/ -NOP -NOS -nocheck STYVAL:USEPRT:NOBLKN:DLNBLK $(DMA_TARGETS)
d87 6
a92 1
#################################################################################
d96 7
a102 1
#################################################################################
d105 2
a106 3
	@@ncvlog -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	\
		-WORK ncwork -NOCOPYRIGHT -UPDATE	\
		-LOGFILE .nclog $(WAVES) $(TARGETS) $(INCDIR)
d108 1
a108 1
#################################################################################
d112 1
a112 1
#################################################################################
d115 3
a117 4
	@@ncelab -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var	 \
		-WORK ncwork -NOCOPYRIGHT $(ACCESS) \
		-LOGFILE .nclog -APPEND_LOG -NOTIMINGCHECKS	 \
		ncwork.$(TOP)
d119 1
a119 1
#################################################################################
d123 5
a127 1
#################################################################################
a128 5
sim:
	@@ncsim -CDSLIB ncwork/cds.lib -HDLVAR ncwork/hdl.var 	\
		-NOCOPYRIGHT -STATUS -LOGFILE .nclog -EXIT	\
		-APPEND_LOG -ERRORMAX 10 -NOKEY -UPDATE	\
		ncwork.$(TOP)
@