head	1.1;
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comment	@# @;


1.1
date	2008.08.25.00.39.32;	author sfielding;	state Exp;
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commitid	118148b1fdaa4567;


desc
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1.1
log
@usbHostSlave - Release 2.0. Seperate host and slave top level modules, in addition the original combined host/slave. Improved cross clock domain synchronisation. Fixed wishbone ack bug. Improved fifo reset synchronisation. Added registers to support USB-PHY, ie USB voltage detect, pull-up enable, and full/low speed selection. Removed Altera SOPC component, removed SystemC testbench, and Aldec simulation. Added Icarus Verilog simulation. Added usbDevice sub-project
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text
@[Project]
Current Flow=Generic
VCS=0
version=1
Current Config=compile

[Configurations]
compile=design0

[Library]
design0=.\design0.LIB

[$LibMap$]
design0=.

[Settings]
FLOW_TYPE=HDL
LANGUAGE=VHDL

[Files]
/EP0.asf=-1
/checkLineState.asf=-1
/EP1Mouse.asf=-1

[Files.Data]
.\src\EP0.asf=State Diagram
.\src\checkLineState.asf=State Diagram
.\src\EP1Mouse.asf=State Diagram

[file_out:/EP0.asf]
/\compile\EP0.v=-1

[file_out:/checkLineState.asf]
/\compile\checkLineState.v=-1

[file_out:/EP1Mouse.asf]
/\compile\EP1Mouse.v=-1

@