head	1.4;
access;
symbols;
locks; strict;
comment	@# @;


1.4
date	2002.11.24.13.58.31;	author jesus;	state Exp;
branches;
next	1.3;

1.3
date	2002.10.21.01.36.55;	author jesus;	state Exp;
branches;
next	1.2;

1.2
date	2002.09.05.04.49.05;	author jesus;	state Exp;
branches;
next	1.1;

1.1
date	2002.08.07.14.47.13;	author jesus;	state Exp;
branches;
next	;


desc
@@


1.4
log
@*** empty log message ***
@
text
@set process "5"
set part "2s200pq208"
set tristate_map "TRUE"
set opt_auto_mode "TRUE"
set opt_best_result "29223.458000"
set dont_lock_lcells "auto"
set input2output "30.000000"
set input2register "20.000000"
set register2output "20.000000"
set register2register "40.000000"
set wire_table "xis215-5_avg"
set encoding "auto"
set edifin_ground_port_names "GND"
set edifin_power_port_names "VCC"
set edif_array_range_extraction_style "%s\[%d:%d\]"

set_xilinx_eqn

load_library xis2

read -technology xis2 {
../../../rtl/vhdl/T80_Pack.vhd
../../../rtl/vhdl/T80_MCode.vhd
../../../rtl/vhdl/T80_ALU.vhd
../../../rtl/vhdl/T80_RegX.vhd
../../../rtl/vhdl/T80.vhd
../../../rtl/vhdl/T80s.vhd
../../../rtl/vhdl/T16450.vhd
../src/MonZ80_leo.vhd
../../../rtl/vhdl/SSRAMX.vhd
../../../rtl/vhdl/DebugSystem.vhd
}

pre_optimize

optimize -hierarchy=auto

optimize_timing

report_area

report_delay

write t80debug_leo.edf
@


1.3
log
@Release 0242
@
text
@d3 1
a3 1
set tristate_map "FALSE"
d7 4
a10 4
set input2output "50.000000"
set input2register "50.000000"
set register2output "50.000000"
set register2register "50.000000"
d25 1
a25 1
../../../rtl/vhdl/T80_Reg.vhd
d30 1
a30 1
../../../rtl/vhdl/SSRAM2.vhd
@


1.2
log
@no message
@
text
@d25 1
@


1.1
log
@Initial import
@
text
@d7 4
a10 4
set input2output "20.000000"
set input2register "20.000000"
set register2output "20.000000"
set register2register "20.000000"
d28 2
a29 2
../src/MonZ80_Sine_leo.vhd
../../../rtl/vhdl/SSRAM.vhd
@