head 1.6; access; symbols spdif_rel_1:1.5 beta_2:1.5 rx_beta_1:1.5; locks; strict; comment @# @; 1.6 date 2007.10.11.19.14.43; author gedra; state Exp; branches; next 1.5; commitid 350b470e761d4567; 1.5 date 2004.07.11.16.19.50; author gedra; state Exp; branches; next 1.4; 1.4 date 2004.06.27.16.16.55; author gedra; state Exp; branches; next 1.3; 1.3 date 2004.06.26.14.14.47; author gedra; state Exp; branches; next 1.2; 1.2 date 2004.06.16.19.03.10; author gedra; state Exp; branches; next 1.1; 1.1 date 2004.06.05.17.17.12; author gedra; state Exp; branches; next ; desc @@ 1.6 log @Code beautification @ text @---------------------------------------------------------------------- ---- ---- ---- WISHBONE SPDIF IP Core ---- ---- ---- ---- This file is part of the SPDIF project ---- ---- http://www.opencores.org/cores/spdif_interface/ ---- ---- ---- ---- Description ---- ---- SPDIF receiver status register ---- ---- ---- ---- ---- ---- To Do: ---- ---- - ---- ---- ---- ---- Author(s): ---- ---- - Geir Drange, gedra@@opencores.org ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2004 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------- -- -- CVS Revision History -- -- $Log: rx_status_reg.vhd,v $ -- Revision 1.5 2004/07/11 16:19:50 gedra -- Bug-fix. -- -- Revision 1.4 2004/06/27 16:16:55 gedra -- Signal renaming and bug fix. -- -- Revision 1.3 2004/06/26 14:14:47 gedra -- Converted to numeric_std and fixed a few bugs. -- -- Revision 1.2 2004/06/16 19:03:10 gedra -- Added channel status decoding. -- -- Revision 1.1 2004/06/05 17:17:12 gedra -- Recevier status register -- -- library ieee; use ieee.std_logic_1164.all; entity rx_status_reg is generic (DATA_WIDTH : integer); port ( wb_clk_i : in std_logic; -- clock status_rd : in std_logic; -- status register read lock : in std_logic; -- signal lock status chas : in std_logic; -- channel A or B select rx_block_start : in std_logic; -- start of block signal ch_data : in std_logic; -- channel status/user data cs_a_en : in std_logic; -- channel status ch. A enable cs_b_en : in std_logic; -- channel status ch. B enable status_dout : out std_logic_vector(DATA_WIDTH - 1 downto 0)); end rx_status_reg; architecture rtl of rx_status_reg is signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0); signal cur_pos : integer range 0 to 255; signal pro_mode : std_logic; begin status_dout <= status_vector when status_rd = '1' else (others => '0'); D32 : if DATA_WIDTH = 32 generate status_vector(31 downto 16) <= (others => '0'); end generate D32; status_vector(0) <= lock; status_vector(15 downto 7) <= (others => '0'); -- extract channel status bits to be used CDAT : process (wb_clk_i, lock) begin if lock = '0' then cur_pos <= 0; pro_mode <= '0'; status_vector(6 downto 1) <= (others => '0'); else if rising_edge(wb_clk_i) then -- bit counter, 0 to 191 if rx_block_start = '1' then cur_pos <= 0; elsif cs_b_en = '1' then -- ch. status #2 comes last, count then cur_pos <= cur_pos + 1; end if; -- extract status bits used in status register if (chas = '0' and cs_b_en = '1') or (chas = '1' and cs_a_en = '1') then case cur_pos is when 0 => -- PRO bit status_vector(1) <= ch_data; pro_mode <= ch_data; when 1 => -- AUDIO bit status_vector(2) <= not ch_data; when 2 => -- emphasis/copy bit if pro_mode = '1' then status_vector(5) <= ch_data; else status_vector(6) <= ch_data; end if; when 3 => -- emphasis if pro_mode = '1' then status_vector(4) <= ch_data; else status_vector(5) <= ch_data; end if; when 4 => -- emphasis if pro_mode = '1' then status_vector(3) <= ch_data; else status_vector(4) <= ch_data; end if; when 5 => -- emphasis if pro_mode = '0' then status_vector(3) <= ch_data; end if; when others => null; end case; end if; end if; end if; end process CDAT; end rtl; @ 1.5 log @Bug-fix. @ text @d48 3 d66 1 a66 1 use ieee.std_logic_1164.all; d68 12 a79 12 entity rx_status_reg is generic (DATA_WIDTH: integer); port ( wb_clk_i: in std_logic; -- clock status_rd: in std_logic; -- status register read lock: in std_logic; -- signal lock status chas: in std_logic; -- channel A or B select rx_block_start: in std_logic; -- start of block signal ch_data: in std_logic; -- channel status/user data cs_a_en: in std_logic; -- channel status ch. A enable cs_b_en: in std_logic; -- channel status ch. B enable status_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0)); d84 4 a87 4 signal status_vector : std_logic_vector(DATA_WIDTH - 1 downto 0); signal cur_pos : integer range 0 to 255; signal pro_mode : std_logic; d89 9 a97 2 status_dout <= status_vector when status_rd = '1' else (others => '0'); a98 7 D32: if DATA_WIDTH = 32 generate status_vector(31 downto 16) <= (others => '0'); end generate D32; status_vector(0) <= lock; status_vector(15 downto 7) <= (others => '0'); d100 2 a101 2 CDAT: process (wb_clk_i, lock) begin d103 3 a105 3 cur_pos <= 0; pro_mode <= '0'; status_vector(6 downto 1) <= (others => '0'); d107 43 a149 43 if rising_edge(wb_clk_i) then -- bit counter, 0 to 191 if rx_block_start = '1' then cur_pos <= 0; elsif cs_b_en = '1' then -- ch. status #2 comes last, count then cur_pos <= cur_pos + 1; end if; -- extract status bits used in status register if (chas = '0' and cs_b_en = '1') or (chas = '1' and cs_a_en = '1') then case cur_pos is when 0 => -- PRO bit status_vector(1) <= ch_data; pro_mode <= ch_data; when 1 => -- AUDIO bit status_vector(2) <= not ch_data; when 2 => -- emphasis/copy bit if pro_mode = '1' then status_vector(5) <= ch_data; else status_vector(6) <= ch_data; end if; when 3 => -- emphasis if pro_mode = '1' then status_vector(4) <= ch_data; else status_vector(5) <= ch_data; end if; when 4 => -- emphasis if pro_mode = '1' then status_vector(3) <= ch_data; else status_vector(4) <= ch_data; end if; when 5 => -- emphasis if pro_mode = '0' then status_vector(3) <= ch_data; end if; when others => null; end case; end if; end if; d151 2 a152 2 end process CDAT; @ 1.4 log @Signal renaming and bug fix. @ text @d48 3 d99 1 a99 1 if lock = '1' then d102 1 @ 1.3 log @Converted to numeric_std and fixed a few bugs. @ text @d48 3 d69 1 a69 1 rx_frame_start: in std_logic; -- start of frame signal d102 1 a102 1 if rx_frame_start = '1' then @ 1.2 log @Added channel status decoding. @ text @d48 3 d56 2 a57 3 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; @ 1.1 log @Recevier status register @ text @d47 4 a50 1 -- $Log$ d60 1 d62 6 a67 1 status_vector: in std_logic_vector(DATA_WIDTH - 1 downto 0); d73 4 d80 61 a140 1 @