head	1.3;
access;
symbols
	rel-0-3-0-rc1:1.3
	stable_0_2_x:1.3.0.4
	stable_0_2_0:1.3
	stable_0_2_0_rc3:1.3
	stable_0_2_0_rc1:1.3
	stable_0_2_0_rc2:1.3
	nog_patch_73:1.3
	nog_patch_72:1.3
	nog_patch_71:1.3
	nog_patch_70:1.3
	nog_patch_69:1.3
	nog_patch_68:1.3
	nog_patch_67:1.3
	nog_patch_66:1.3
	nog_patch_65:1.3
	nog_patch_64:1.3
	nog_patch_63:1.3
	nog_patch_62:1.3
	nog_patch_61:1.3
	nog_patch_60:1.3
	nog_patch_59:1.3
	nog_patch_58:1.3
	nog_patch_57:1.3
	nog_patch_56:1.3
	nog_patch_55:1.3
	nog_patch_54:1.3
	nog_patch_53:1.3
	nog_patch_52:1.3
	nog_patch_51:1.3
	nog_patch_50:1.3
	nog_patch_49:1.3
	nog_patch_48:1.3
	nog_patch_47:1.3
	nog_patch_46:1.3
	nog_patch_45:1.3
	nog_patch_44:1.3
	nog_patch_43:1.3
	nog_patch_42:1.3
	nog_patch_41:1.3
	nog_patch_40:1.3
	nog_patch_39:1.3
	nog_patch_38:1.3
	nog_patch_37:1.3
	nog_patch_36:1.3
	nog_patch_35:1.3
	nog_patch_34:1.3
	nog_patch_33:1.3
	stable_0_1_x:1.3.0.2
	stable_0_1_0:1.3;
locks; strict;
comment	@# @;


1.3
date	2002.08.02.11.35.53;	author markom;	state Exp;
branches;
next	1.2;

1.2
date	2002.08.02.11.17.36;	author markom;	state Exp;
branches;
next	1.1;

1.1
date	2002.08.01.17.12.21;	author markom;	state Exp;
branches;
next	;


desc
@@


1.3
log
@sfor instruction replaced by conditional cmov
@
text
@#
# very draft timing table for FPGA Virtex, sg -5
# size is in gates, delay in ns
#
# instruction_name size_normal size_immediate delay_normal delay_immediate
#

add   30.   15.   8.    4.
sub   30.   15.   8.    4.
and   5.    0.    1.    0.
or    5.    0.    1.    0.
xor   10.   2.    1.    0.5
mul   700.  200.  12.   5.
srl   100.  1.    24.   12.
sll   100.  1.    24.   12.
sra   100.  1.    24.   12.

lb    50.   50.   5.    5.
lh    50.   50.   5.    5.
lw    50.   50.   5.    5.
sb    50.   50.   5.    5.
sh    50.   50.   5.    5.
sw    50.   50.   5.    5.

sfeq  20.   10.   5.    2.
sfne  20.   10.   5.    2.
sfle  30.   10.   8.    4.
sflt  30.   10.   8.    4.
sfgt  30.   10.   8.    4.
sfge  30.   10.   8.    4.
bf    50.   50.   1.    1.

lrbb  60.   60.   1.    1.
cmov  15.   15.   5.    2.
reg   60.   60.   1.    1.

call  100.  100.  3.    3.
nop   0.    0.    0.    0.
  

@


1.2
log
@problems with LRBB removal solved
@
text
@a30 1
sfor  1.    0.5   1.    0.5
@


1.1
log
@new BB joining type; BBID_END added; virtex.tim sample cuc timings
@
text
@d10 2
a11 2
and   5.    1.    1.    0.5
or    5.    1.    1.    0.5
@