head 1.8; access; symbols rel-0-3-0-rc1:1.8 stable_0_2_x:1.7.0.4 stable_0_2_0:1.7 stable_0_2_0_rc3:1.7 stable_0_2_0_rc1:1.7 stable_0_2_0_rc2:1.7 nog_patch_73:1.7 nog_patch_72:1.7 nog_patch_71:1.7 nog_patch_70:1.7 nog_patch_69:1.7 nog_patch_68:1.7 nog_patch_67:1.7 nog_patch_66:1.7 nog_patch_65:1.7 nog_patch_64:1.7 nog_patch_63:1.7 nog_patch_62:1.7 nog_patch_61:1.7 nog_patch_60:1.7 nog_patch_59:1.7 nog_patch_58:1.7 nog_patch_57:1.7 nog_patch_56:1.7 nog_patch_55:1.7 nog_patch_54:1.7 nog_patch_53:1.7 nog_patch_52:1.7 nog_patch_51:1.7 nog_patch_50:1.7 nog_patch_49:1.7 nog_patch_48:1.7 nog_patch_47:1.7 nog_patch_46:1.7 nog_patch_45:1.7 nog_patch_44:1.7 nog_patch_43:1.7 nog_patch_42:1.7 nog_patch_41:1.7 nog_patch_40:1.7 nog_patch_39:1.7 nog_patch_38:1.7 nog_patch_37:1.7 nog_patch_36:1.7 nog_patch_35:1.7 nog_patch_34:1.7 nog_patch_33:1.7 stable_0_1_x:1.7.0.2 stable_0_1_0:1.7 tn_m001:1.6; locks; strict; comment @# @; 1.8 date 2008.09.06.18.08.03; author jeremybennett; state Exp; branches; next 1.7; commitid 6b848c2c6564567; 1.7 date 2002.10.29.09.48.55; author simons; state Exp; branches; next 1.6; 1.6 date 2001.11.23.08.51.55; author simons; state Exp; branches; next 1.5; 1.5 date 2001.11.13.10.43.05; author markom; state Exp; branches; next 1.4; 1.4 date 2001.10.24.13.31.32; author markom; state Exp; branches; next 1.3; 1.3 date 2001.10.04.10.17.05; author erez; state Exp; branches; next 1.2; 1.2 date 2001.09.07.20.16.08; author simons; state Exp; branches; next 1.1; 1.1 date 2001.05.03.04.26.30; author lampret; state Exp; branches; next ; desc @@ 1.8 log @These are the changes to allow or1ksim to build as a library as well as a standalone simulator. The concept of a "generic" peripheral is added, which will commuicate with an external model via upcalls. @ text @ Or1ksim Test Suite ================== This directory includes some test case programs that should be used to verify correct operation of the or1ksim, OR32 GCC and OR32 GNU Binutils. Pre-requisites ============== The GNU toolchain for OpenRISC 1000 is required. Instructions how to build these GNU tools can be found on www.opencores.org Or1ksim must be built and installed (see ../README) Configuration and Running ========================= The installation uses standard GNU autoconf/automake files. Generic instructions on this are in the INSTALL file. Or1ksim Test Suite should be capable of being built in a separate directory - but for now that is broken. All programs are built and checked from the test directory by: $ ./configure --target=or32-uclinux --host=or32 $ make all $ make check !!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE !!! !!! undefined in cpu/or1k/except.h. This is the default behavior !!! All tests should exit with: MTSPR(0x1234, deaddead); syscall exit(0) If the test fails, it should print as much output as possible about the failure. Overall the test script checks for the above two lines, and can be fooled by intervening log output. The Tests ========= A total of 20 tests including: dhry: Dhrystone 2.1: a benchmark modified to use simulator's timing facility. basic: a test for all instructions and all GPRs. test1: a test for "all" instructions and their combinations. pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things. cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). dma: a test of DMA in normal (software) mode. compress: UNIX compressed modified not to use libc calls. mul: Test l.mul, l.mac and l.macrc instructions. Upated by Jeremy Bennett (jeremy@@jeremybennett.com) 9 June 2008 @ 1.7 log @or32-uclinux tool chain have to be used to build the testbench. @ text @d1 2 a2 2 This directory includes some test case programs that should be used to verify correct operation of the or1ksim, OR32 GCC and OR32 GNU Binutils. a3 1 All programs are built and checked by: d5 2 a6 2 ./configure --target=or32-uclinux make all check a7 1 You need to have all GNU OR32 tools installed and in the path. d9 27 a35 2 !!! For all test cases, or1ksim should be built with ONLY_VIRTUAL_MACHINE undefined in cpu/or1k/except.h !!! a37 2 MTSPR(0x1234, deaddead); syscall exit(0) d39 2 a40 1 If the test fails, it should print as much output as possible about the failure. d42 21 a62 7 dhry: Dhrystone 2.1: a benchmark modified to use simulator's timing facility. basic: a test for all instructions and all GPRs. test1: a test for "all" instructions and their combinations. pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things. cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). dma: a test of DMA in normal (software) mode. d64 5 a68 1 mul: Test l.mul, l.mac and l.macrc instructions. @ 1.6 log @Configuration command description added. @ text @d6 1 a6 1 ./configure --target=or32-rtems @ 1.5 log @added VAPI for uart; uart 16550 support, some bugs fixed @ text @d5 2 d8 1 @ 1.4 log @added missing support files @ text @d4 3 a6 2 All programs are built from root directories. You need to have all GNU OR32 tools installed and in path. d11 1 a11 92 Dhrystone 2.1: a benchmark modified to use simulator's timing facility. It should finish with exit(0). ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ running simulation: # ./sim testbench/dhrystone/dhry.or32 (sim) run -1 hush MTSPR(0x1234, 20070); MTSPR(0x1234, 20013); MTSPR(0x1234, 7); MTSPR(0x1234, 30010); MTSPR(0x1234, 30010); MTSPR(0x1234, 8); MTSPR(0x1234, 20020); MTSPR(0x1234, 9); syscall exit(0) (sim) stdout.txt should read like this: Execution starts, 20 runs through Dhrystone Begin Time = 549 End Time = 22701 OR1K at 200 MHz Microseconds for one run through Dhrystone: 110 us / 20 runs Dhrystones per Second: 181 basic: a test for all instructions and all GPRs. If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/basic.or32 (sim) run -1 hush UART 0 RX EOF detected. Shutting down to prevent endless loop. MTSPR(0x1234, ffff0012); MTSPR(0x1234, 12352af7); MTSPR(0x1234, 7ffffffe); MTSPR(0x1234, ffffa5a7); MTSPR(0x1234, fffff); MTSPR(0x1234, 2800); MTSPR(0x1234, a); MTSPR(0x1234, deaddead); syscall exit(0) (sim) Standard output: RESULT: deaddead test1: a test for "all" instructions and their combinations. If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/cbasic.or32 (sim) run -1 hush MTSPR(0x1234, ffffffda); MTSPR(0x1234, ffffffc5); MTSPR(0x1234, 6805); MTSPR(0x1234, ffff97f9); MTSPR(0x1234, ffff97f9); MTSPR(0x1234, 7a77952e); MTSPR(0x1234, 81e5e000); MTSPR(0x1234, 74); MTSPR(0x1234, 74); MTSPR(0x1234, 74); MTSPR(0x1234, 1); MTSPR(0x1234, d7c); MTSPR(0x1234, 74); MTSPR(0x1234, 74); MTSPR(0x1234, 74); MTSPR(0x1234, ffffffff); MTSPR(0x1234, d7a); MTSPR(0x1234, d7a); MTSPR(0x1234, deaddead); syscall exit(0) (sim) Standard output: RESULT: deaddead pic: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/pic.or32 (sim) run -1 hush ... ... ... MTSPR(0x1234, 178); MTSPR(0x1234, 178); a13 103 (sim) Standard output: RESULT: deaddead excpt: a test of l.sys instruction. Checks all the delay slot issues ind other things. If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/excpt.or32 (sim) run -1 hush UART 0 RX EOF detected. Shutting down to prevent endless loop. Exception 0xc00 (System Call): Iqueue[0].insn_addr: 0xc74 Eff ADDR: 0x0 pc: 0xc74 pcnext: 0xc78 MTSPR(0x1234, 1); MTSPR(0x1234, 1); MTSPR(0x1234, 1c); MTSPR(0x1234, 1); MTSPR(0x1234, 3); MTSPR(0x1234, deaddead); syscall exit(0) (sim) Standard output: RESULT: deaddead cfg: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/cfg.or32 (sim) run -1 hush MTSPR(0x1234, 0); MTSPR(0x1234, e83f); MTSPR(0x1234, 0); MTSPR(0x1234, 5); MTSPR(0x1234, 20); MTSPR(0x1234, 1d); MTSPR(0x1234, 1d); MTSPR(0x1234, 1d); MTSPR(0x1234, 1d); MTSPR(0x1234, 8); MTSPR(0x1234, 1); MTSPR(0x1234, deaddead); syscall exit(0) (sim) Standard output: RESULT: deaddead dma: a test of DMA in normal (software) mode. If everything is ok, RESULT == 0xdeadead. ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: # ./sim testbench/dma.or32 (sim) run 1000000 hush MTSPR(0x1234, 1); MTSPR(0x1234, 6); MTSPR(0x1234, a); MTSPR(0x1234, deaddead); syscall exit(0) (sim) Standard output: RESULT: deaddead compress: UNIX compressed modified not to use libc calls. Should finish with exit(0). ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: ./sim testbench/compress/mycompress.or32 (sim) run -1 hush Interrupt reported. Interrupt reported. syscall exit(0) (sim) Standard output: main: bytes_out 3... hsize 5003 main: hshift 4... main: bytes_out 3... main: hsize_reg 5003... main: before compress 1... main: compressing 1... main: compressing 2... main: compressing 3... main: compressing 997... main: compressing 998... main: compressing 999... main: output... main: end... mul: Test l.mul, l.mac and l.macrc instructions. Should finish with exit(0). ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Simulation: ./sim testbench/mul.or32 (sim) run -1 hush MTSPR(0x1234, deadbeef); syscall exit(0) (sim) d15 1 a15 1 Standard output: d17 9 a25 4 0xa6312f33, expected 0xa6312f33 0x0d4de375, expected 0x0d4de375 0x61ab48dc, expected 0x61ab48dc Test succesful. @ 1.3 log @Added test5 for DMA @ text @d4 2 a5 3 All programs should be built inside their directories (ie. dhrystone should be built inside testbench/dhrystone). You need to have all GNU OR32 tools installed and in path. All makefiles assume or32-rtems target. d16 1 a16 1 (sim) run 1000000 hush d38 1 a38 1 test0: a test for all instructions and all GPRs. If everything is ok, RESULT == 0xdeadead. d42 2 a43 2 # ./sim testbench/test0/test0.or32 (sim) run 1000000000 hush d64 2 a65 2 # ./sim testbench/test1/test1.or32 (sim) run 100000000 hush d91 1 a91 1 test2: a test for PIC and TICK timer. All three modes of TICK timer are tested and interrupt is enabled and disabled in PIC. If everything is ok, RESULT == 0xdeadead. d95 2 a96 2 # ./sim testbench/test2/test2.or32 (sim) run 100000000 hush d109 1 a109 1 test3: a test of l.sys instruction. Checks all the delay slot issues ind other things. If everything is ok, RESULT == 0xdeadead. d113 2 a114 2 # ./sim testbench/test3/test3.or32 (sim) run 1000000 hush d130 1 a130 1 test4: a test of SPRs (SPR_VR, SPR_CPUCFGR, SPR_DMMUCFGR, SPR_IMMUCFGR, SPR_DCCFGR, SPR_ICCFGR, SPR_DCFGR, SPR_PCCFGR). If everything is ok, RESULT == 0xdeadead. d134 2 a135 2 # ./sim testbench/test4/test4.or32 (sim) run 1000000 hush d154 1 a154 1 test5: a test of DMA in normal (software) mode. If everything is ok, RESULT == 0xdeadead. d158 1 a158 1 # ./sim testbench/test5/test5.or32 d176 1 a176 1 (sim) run 100000000 hush d199 15 @ 1.2 log @New test added. @ text @d155 16 @ 1.1 log @Description of all test cases (at least working one). @ text @d39 21 d88 63 @