head	1.1;
branch	1.1.1;
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	v001:1.1.1.1
	kongzilee:1.1.1;
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comment	@# @;


1.1
date	2006.01.25.13.44.09;	author kongzilee;	state Exp;
branches
	1.1.1.1;
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commitid	660443d7809e4567;

1.1.1.1
date	2006.01.25.13.44.09;	author kongzilee;	state Exp;
branches;
next	;
commitid	660443d7809e4567;


desc
@@


1.1
log
@Initial revision
@
text
@ -------  FILE NO #1 : oks8sim.l -------
Sat Jan 07 09:09:49 2006


     SAM8 Assembler for Reduced Instruction  Ver. 2.10T(Win32)
         Copyright (c) 1999 Samsung Electronics Co.

    --------------------------------------------------------------------

                       Source File Name : oks8sim.src
                       Output File Name : oks8sim.o
                       List File Name   : oks8sim.l


    1                    	.list   on
    2                    
    3                    	.list on
    4                    
    5                    ;--------------<< Interrupt Vector Address >>
    6  0000              .ORG 0000H
    7                    
    8  0000   01 51      .VECTOR 00H,INT_4208		; KS86C4208 has only one interrupt vector
    9                    
   10  0100              .ORG 0100H
   11                    
   12  0100              INITIAL:
   13                    
   14  0100   E6 DF 00    LD SYM, #00H
   15  0103   E6 DC A2    LD BTCON, #10100010B
   16  0106   E6 D4 18    LD CLKCON, #00011000B	; non-divided CPU clock
   17  0109   E6 D9 C0    LD SP, #0C0H			; 4208 -> 00~BF (After decrease, push data)
   18                    ;--------------<< Port Initialization >>
   19  010C   E6 E6 00    LD P0CONH, #0		; input
   20  010F   E6 E7 00    LD P0CONL, #0		; input
   21  0112   E6 E8 FF    LD P0PUR, #0FFH		; pull-up enable
   22  0115   E6 E9 50    LD P1CON, #50H		; input, EXT.INT enable
   23  0118   E6 EA F0    LD P1PND, #0F0H		; pull-up enable
   24  011B   E6 EB 00    LD P2CONH, #0		; input
   25  011E   E6 EC 00    LD P2CONL, #0		; input
   26  0121   E6 ED FF    LD P2PUR, #0FFH		; pull-up enable
   27  0124   E6 EE 00    LD P3CON, #0		; push-pull output
   28                    ;--------------<< Timer 0 Setting >>
   29  0127   E6 D1 41    LD T0DATA, #41H		; interrupt interval --1.667msec (10MHz base)
   30  012A   E6 D3 42    LD T0CONL, #01000010B	; Timer 0 match output
   31                    ;--------------<< RAM Area Clear >>
   32  012D   0C 00       LD R0, #0		; RAM clear area setting
   33  012F               RAM_CLR:
   34  012F   B1 C0       CLR @@R0
   35  0131   0E          INC R0
   36  0132   A6 C0 BF    CP R0, #0BFH		; general register area -> 00H~BFH
   37                     ;JR ULE, RAM_CLR
   38  0135   0B F8       JR F, RAM_CLR
   39                    ;--------------<< Initialize Other Register >>
   40                    ;，
   41                    ;，
   42                    ;，
   43  0137   9F          EI
   44                    
   45                    ;--------------<< Main Loop >>
   46  0138               MAIN:
   47  0138   FF          NOP
   48  0139   0C 33       LD R0, #33H
   49                    ;，
   50                    ;，
   51                    ;，
   52  013B   F6 01 44    CALL SUB_ROUTINE0	; subroutine call
   53                    ;，
   54                    ;，
   55                    ;，
   56  013E   F6 01 4B    CALL SUB_ROUTINE1	; subroutine call
   57                    ;，
   58                    ;，
   59                    ;，
   60  0141   8D 01 38    JP MAIN
   61                    
   62                    ;--------------<< Subroutine >>
   63  0144              SUB_ROUTINE0:
   64  0144   FF          NOP
   65  0145   A7 00 04 11 LDC R0, 1104H
   66                    ;，
   67                    ;，
   68                    ;，
   69  0149   6F          IDLE
   70  014A   AF          RET
   71                    
   72  014B              SUB_ROUTINE1:
   73  014B   FF          NOP
   74  014C   A7 01 04 11 LDE R0, 1104H
   75                    ;，
   76                    ;，
   77                    ;，
   78  0150   AF          RET
   79                    
   80                    ;--------------<< Interrupt Service Routine >>
   81  0151              INT_4208:
   82                    
   83  0151   08 D3       LD R0, T0CONL		; KS86C4208 has just one interrupt vector
   84  0153   56 C0 03    AND R0, #00000011B	; only Timer 0 match interrupt enable
   85  0156   A6 C0 03    CP R0, #00000011B
   86  0159   6D 01 5C    JP EQ, INT_TIMER0	; T0CON¨s pending bit & INT. enable bit check
   87  015C               INT_TIMER0:
   88  015C   56 D3 FE    AND T0CONL, #11111110B	; pending clear
   89                    ;，
   90                    ;，
   91                    ;，
   92  015F   A7 00 04 11 LDC R0, 1104H
   93  0163   A7 01 04 11 LDE R0, 1104H
   94  0167   A7 02 00 10 LDC R0, #1000H[RR2]
   95  016B   A7 03 00 10 LDE R0, #1000H[RR2]
   96  016F   E2 06       LDCD R0, @@RR6
   97  0171   E2 07       LDED R0, @@RR6
   98                    
   99  0173   BF          IRET
  100                    ;，
  101                    ;，
  102                    ;，
  103                    


Total 103 Lines Assembled - 0 Errors, 0 Warnings
Total code size 0x76


@


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