head	1.4;
access;
symbols
	V3_0:1.4;
locks; strict;
comment	@:: @;


1.4
date	2002.07.03.05.13.16;	author rhoads;	state Exp;
branches;
next	1.3;

1.3
date	2002.06.16.22.42.23;	author rhoads;	state Exp;
branches;
next	1.2;

1.2
date	2002.02.06.21.14.22;	author rhoads;	state Exp;
branches;
next	1.1;

1.1
date	2001.12.26.19.59.20;	author rhoads;	state Exp;
branches;
next	;


desc
@@


1.4
log
@Updated
@
text
@add list /u1/*
#add list /u1/u1_cpu/*
#add list /u1/u1_cpu/u8_mult/*
#add list /u1/u1_cpu/pc /u1/u1_cpu/opcode /u1/*
#add list /u1/u1_cpu/u3_control/*
#add list /u1/u1_cpu/u8_mult/*
SetListStyle nodelta collapse
SetListInterval 0us 1ms
@


1.3
log
@Altera
@
text
@a0 1
#add list /u1/pc /u1/opcode /u1/*
d2 5
a6 3
#add list /u1/u4_reg_bank/bank1/*
#add list /u1/u3_control/*
#add list /u1/u8_mult/*
@


1.2
log
@Added comments
@
text
@d1 2
a2 2
add list /u1/pc /u1/opcode /u1/*
#add list /tbench/*
d6 1
a6 1
#SetListStyle nodelta collapse
@


1.1
log
@Made writes 4 cycles, improved mem_ctrl.vhd
@
text
@d3 4
a6 1
SetListStyle nodelta collapse
@