head	1.9;
access;
symbols
	V3_0:1.9
	V2_1:1.7
	Version_1_0:1.1.1.1
	arelease:1.1.1.1
	avendor:1.1.1;
locks; strict;
comment	@# @;


1.9
date	2006.03.06.02.07.03;	author rhoads;	state Exp;
branches;
next	1.8;
commitid	699f440b99354567;

1.8
date	2004.06.26.16.12.38;	author rhoads;	state Exp;
branches;
next	1.7;

1.7
date	2002.06.25.03.41.56;	author rhoads;	state Exp;
branches;
next	1.6;

1.6
date	2002.06.16.22.38.06;	author rhoads;	state Exp;
branches;
next	1.5;

1.5
date	2002.05.30.02.19.51;	author rhoads;	state Exp;
branches;
next	1.4;

1.4
date	2002.03.11.02.18.58;	author rhoads;	state Exp;
branches;
next	1.3;

1.3
date	2002.02.06.21.03.26;	author rhoads;	state Exp;
branches;
next	1.2;

1.2
date	2001.12.22.21.51.20;	author rhoads;	state Exp;
branches;
next	1.1;

1.1
date	2001.05.17.21.22.53;	author rhoads;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2001.05.17.21.22.53;	author rhoads;	state Exp;
branches;
next	;


desc
@@


1.9
log
@Major changes -- updated to Plasma Version 3
@
text
@---------------------------------------------------------------------
-- TITLE: Program Counter Next
-- AUTHOR: Steve Rhoads (rhoadss@@yahoo.com)
-- DATE CREATED: 2/8/01
-- FILENAME: pc_next.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
--    Software 'as is' without warranty.  Author liable for nothing.
-- DESCRIPTION:
--    Implements the Program Counter logic.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;

entity pc_next is
   port(clk         : in std_logic;
        reset_in    : in std_logic;
        pc_new      : in std_logic_vector(31 downto 2);
        take_branch : in std_logic;
        pause_in    : in std_logic;
        opcode25_0  : in std_logic_vector(25 downto 0);
        pc_source   : in pc_source_type;
        pc_future   : out std_logic_vector(31 downto 2);
        pc_current  : out std_logic_vector(31 downto 2);
        pc_plus4    : out std_logic_vector(31 downto 2));
end; --pc_next

architecture logic of pc_next is
   signal pc_reg : std_logic_vector(31 downto 2); 
begin

pc_select: process(clk, reset_in, pc_new, take_branch, pause_in, 
                 opcode25_0, pc_source, pc_reg)
   variable pc_inc      : std_logic_vector(31 downto 2);
   variable pc_next : std_logic_vector(31 downto 2);
begin
   pc_inc := bv_increment(pc_reg);  --pc_reg+1

   case pc_source is
   when FROM_INC4 =>
      pc_next := pc_inc;
   when FROM_OPCODE25_0 =>
      pc_next := pc_reg(31 downto 28) & opcode25_0;
   when FROM_BRANCH | FROM_LBRANCH =>
      if take_branch = '1' then
         pc_next := pc_new;
      else
         pc_next := pc_inc;
      end if;
   when others =>
      pc_next := pc_inc;
   end case;

   if pause_in = '1' then
      pc_next := pc_reg;
   end if;

   if reset_in = '1' then
      pc_reg <= ZERO(31 downto 2);
      pc_next := pc_reg;
   elsif rising_edge(clk) then
      pc_reg <= pc_next;
   end if;

   pc_future <= pc_next;
   pc_current <= pc_reg;
   pc_plus4 <= pc_inc;
end process;

end; --logic
@


1.8
log
@Reset all registers, constants now upper case.
@
text
@d17 10
a26 9
   port(clk          : in std_logic;
        reset_in     : in std_logic;
        pc_new       : in std_logic_vector(31 downto 2);
        take_branch  : in std_logic;
        pause_in     : in std_logic;
        opcode25_0   : in std_logic_vector(25 downto 0);
        pc_source    : in pc_source_type;
        pc_out       : out std_logic_vector(31 downto 0);
        pc_out_plus4 : out std_logic_vector(31 downto 0));
d33 1
a33 1
pc_next: process(clk, reset_in, pc_new, take_branch, pause_in, 
d35 2
a36 1
   variable pc_inc, pc_next : std_logic_vector(31 downto 2);
d61 1
d66 3
a68 2
   pc_out <= pc_reg & "00";
   pc_out_plus4 <= pc_inc & "00";
a71 1

@


1.7
log
@better pause for pipeline
@
text
@d29 1
a29 3
--   type pc_source_type is (from_inc4, from_opcode25_0, from_branch, 
--      from_lbranch);
   signal pc_reg : std_logic_vector(31 downto 2); --:= ZERO(31 downto 2);
d39 1
a39 1
   when from_inc4 =>
d41 1
a41 1
   when from_opcode25_0 =>
d43 1
a43 1
   when others =>   --from_branch | from_lbranch =>
d49 2
@


1.6
log
@Ascyn reset
@
text
@d39 1
d42 1
a42 5
      if pause_in = '0' then
         pc_next := pc_inc;
      else
	     pc_next := pc_reg;
      end if;
d52 5
@


1.5
log
@Altera
@
text
@d56 2
a57 4
      pc_next := ZERO(31 downto 2);
   end if;

   if rising_edge(clk) then
@


1.4
log
@Renamed M-lite to Plasma
@
text
@a38 1
   pc_next := pc_reg;
d43 2
d48 1
a48 1
   when from_branch | from_lbranch =>
a53 1
   when others =>
@


1.3
log
@Changed name to M-lite to avoid trademark issues.
@
text
@d6 1
a6 1
-- PROJECT: M-lite CPU core
@


1.2
log
@JAL now correctly sets r31 to instruction AFTER branch delay slot.  Fixed interrupts.
@
text
@d6 1
a6 1
-- PROJECT: MIPS CPU core
d14 1
a14 1
use work.mips_pack.all;
@


1.1
log
@Initial revision
@
text
@d24 2
a25 1
        pc_out       : out std_logic_vector(31 downto 0));
d35 1
a35 2
                 opcode25_0, pc_source,
                 pc_reg)
d64 1
@


1.1.1.1
log
@MIPS-lite CPU core
@
text
@@