head 1.18; access; symbols V3_0:1.14 V2_1:1.11; locks; strict; comment @# @; 1.18 date 2008.01.28.00.28.15; author rhoads; state Exp; branches; next 1.17; commitid 6675479d219d4567; 1.17 date 2007.12.15.16.14.39; author rhoads; state Exp; branches; next 1.16; commitid 64074763fd6d4567; 1.16 date 2007.04.20.14.45.56; author rhoads; state Exp; branches; next 1.15; commitid 63e14628d21d4567; 1.15 date 2007.02.14.18.56.07; author rhoads; state Exp; branches; next 1.14; commitid 5b6a45d35b424567; 1.14 date 2006.03.06.02.07.03; author rhoads; state Exp; branches; next 1.13; commitid 699f440b99354567; 1.13 date 2004.11.11.03.24.24; author rhoads; state Exp; branches; next 1.12; 1.12 date 2004.06.26.16.08.06; author rhoads; state Exp; branches; next 1.11; 1.11 date 2004.06.08.02.44.11; author rhoads; state Exp; branches; next 1.10; 1.10 date 2003.12.10.02.20.13; author rhoads; state Exp; branches; next 1.9; 1.9 date 2002.07.04.22.42.58; author rhoads; state Exp; branches; next 1.8; 1.8 date 2002.07.03.05.12.29; author rhoads; state Exp; branches; next 1.7; 1.7 date 2002.06.25.03.36.35; author rhoads; state Exp; branches; next 1.6; 1.6 date 2002.06.16.22.40.19; author rhoads; state Exp; branches; next 1.5; 1.5 date 2002.06.06.03.19.37; author rhoads; state Exp; branches; next 1.4; 1.4 date 2002.05.30.02.11.24; author rhoads; state Exp; branches; next 1.3; 1.3 date 2002.03.13.13.24.30; author rhoads; state Exp; branches; next 1.2; 1.2 date 2002.03.11.02.18.58; author rhoads; state Exp; branches; next 1.1; 1.1 date 2002.02.06.20.59.11; author rhoads; state Exp; branches; next ; desc @@ 1.18 log @Added eth_dma @ text @--------------------------------------------------------------------- -- TITLE: Plasma Misc. Package -- AUTHOR: Steve Rhoads (rhoadss@@yahoo.com) -- DATE CREATED: 2/15/01 -- FILENAME: mlite_pack.vhd -- PROJECT: Plasma CPU core -- COPYRIGHT: Software placed into the public domain by the author. -- Software 'as is' without warranty. Author liable for nothing. -- DESCRIPTION: -- Data types, constants, and add functions needed for the Plasma CPU. --------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; package mlite_pack is constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"; constant ONES : std_logic_vector(31 downto 0) := "11111111111111111111111111111111"; --make HIGH_Z equal to ZERO if compiler complains constant HIGH_Z : std_logic_vector(31 downto 0) := "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; subtype alu_function_type is std_logic_vector(3 downto 0); constant ALU_NOTHING : alu_function_type := "0000"; constant ALU_ADD : alu_function_type := "0001"; constant ALU_SUBTRACT : alu_function_type := "0010"; constant ALU_LESS_THAN : alu_function_type := "0011"; constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100"; constant ALU_OR : alu_function_type := "0101"; constant ALU_AND : alu_function_type := "0110"; constant ALU_XOR : alu_function_type := "0111"; constant ALU_NOR : alu_function_type := "1000"; subtype shift_function_type is std_logic_vector(1 downto 0); constant SHIFT_NOTHING : shift_function_type := "00"; constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01"; constant SHIFT_RIGHT_SIGNED : shift_function_type := "11"; constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10"; subtype mult_function_type is std_logic_vector(3 downto 0); constant MULT_NOTHING : mult_function_type := "0000"; constant MULT_READ_LO : mult_function_type := "0001"; constant MULT_READ_HI : mult_function_type := "0010"; constant MULT_WRITE_LO : mult_function_type := "0011"; constant MULT_WRITE_HI : mult_function_type := "0100"; constant MULT_MULT : mult_function_type := "0101"; constant MULT_SIGNED_MULT : mult_function_type := "0110"; constant MULT_DIVIDE : mult_function_type := "0111"; constant MULT_SIGNED_DIVIDE : mult_function_type := "1000"; subtype a_source_type is std_logic_vector(1 downto 0); constant A_FROM_REG_SOURCE : a_source_type := "00"; constant A_FROM_IMM10_6 : a_source_type := "01"; constant A_FROM_PC : a_source_type := "10"; subtype b_source_type is std_logic_vector(1 downto 0); constant B_FROM_REG_TARGET : b_source_type := "00"; constant B_FROM_IMM : b_source_type := "01"; constant B_FROM_SIGNED_IMM : b_source_type := "10"; constant B_FROM_IMMX4 : b_source_type := "11"; subtype c_source_type is std_logic_vector(2 downto 0); constant C_FROM_NULL : c_source_type := "000"; constant C_FROM_ALU : c_source_type := "001"; constant C_FROM_SHIFT : c_source_type := "001"; --same as alu constant C_FROM_MULT : c_source_type := "001"; --same as alu constant C_FROM_MEMORY : c_source_type := "010"; constant C_FROM_PC : c_source_type := "011"; constant C_FROM_PC_PLUS4 : c_source_type := "100"; constant C_FROM_IMM_SHIFT16: c_source_type := "101"; constant C_FROM_REG_SOURCEN: c_source_type := "110"; subtype pc_source_type is std_logic_vector(1 downto 0); constant FROM_INC4 : pc_source_type := "00"; constant FROM_OPCODE25_0 : pc_source_type := "01"; constant FROM_BRANCH : pc_source_type := "10"; constant FROM_LBRANCH : pc_source_type := "11"; subtype branch_function_type is std_logic_vector(2 downto 0); constant BRANCH_LTZ : branch_function_type := "000"; constant BRANCH_LEZ : branch_function_type := "001"; constant BRANCH_EQ : branch_function_type := "010"; constant BRANCH_NE : branch_function_type := "011"; constant BRANCH_GEZ : branch_function_type := "100"; constant BRANCH_GTZ : branch_function_type := "101"; constant BRANCH_YES : branch_function_type := "110"; constant BRANCH_NO : branch_function_type := "111"; -- mode(32=1,16=2,8=3), signed, write subtype mem_source_type is std_logic_vector(3 downto 0); constant MEM_FETCH : mem_source_type := "0000"; constant MEM_READ32 : mem_source_type := "0100"; constant MEM_WRITE32 : mem_source_type := "0101"; constant MEM_READ16 : mem_source_type := "1000"; constant MEM_READ16S : mem_source_type := "1010"; constant MEM_WRITE16 : mem_source_type := "1001"; constant MEM_READ8 : mem_source_type := "1100"; constant MEM_READ8S : mem_source_type := "1110"; constant MEM_WRITE8 : mem_source_type := "1101"; function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector; function bv_negate(a : in std_logic_vector) return std_logic_vector; function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector; function bv_inc(a : in std_logic_vector ) return std_logic_vector; -- For Altera COMPONENT lpm_ram_dp GENERIC ( lpm_width : NATURAL; lpm_widthad : NATURAL; rden_used : STRING; intended_device_family : STRING; lpm_indata : STRING; lpm_wraddress_control : STRING; lpm_rdaddress_control : STRING; lpm_outdata : STRING; use_eab : STRING; lpm_type : STRING); PORT ( wren : IN STD_LOGIC ; wrclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); data : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (lpm_widthad-1 DOWNTO 0)); END COMPONENT; -- For Altera component LPM_RAM_DQ generic ( LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 LPM_NUMWORDS : natural := 0; LPM_INDATA : string := "REGISTERED"; LPM_ADDRESS_CONTROL: string := "REGISTERED"; LPM_OUTDATA : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DQ"; USE_EAB : string := "OFF"; INTENDED_DEVICE_FAMILY : string := "UNUSED"; LPM_HINT : string := "UNUSED"); port ( DATA : in std_logic_vector(LPM_WIDTH-1 downto 0); ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0); INCLOCK : in std_logic := '0'; OUTCLOCK : in std_logic := '0'; WE : in std_logic; Q : out std_logic_vector(LPM_WIDTH-1 downto 0)); end component; -- For Xilinx component RAM16X1D -- synthesis translate_off generic (INIT : bit_vector := X"16"); -- synthesis translate_on port (DPO : out STD_ULOGIC; SPO : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; D : in STD_ULOGIC; DPRA0 : in STD_ULOGIC; DPRA1 : in STD_ULOGIC; DPRA2 : in STD_ULOGIC; DPRA3 : in STD_ULOGIC; WCLK : in STD_ULOGIC; WE : in STD_ULOGIC); end component; component pc_next port(clk : in std_logic; reset_in : in std_logic; pc_new : in std_logic_vector(31 downto 2); take_branch : in std_logic; pause_in : in std_logic; opcode25_0 : in std_logic_vector(25 downto 0); pc_source : in pc_source_type; pc_future : out std_logic_vector(31 downto 2); pc_current : out std_logic_vector(31 downto 2); pc_plus4 : out std_logic_vector(31 downto 2)); end component; component mem_ctrl port(clk : in std_logic; reset_in : in std_logic; pause_in : in std_logic; nullify_op : in std_logic; address_pc : in std_logic_vector(31 downto 2); opcode_out : out std_logic_vector(31 downto 0); address_in : in std_logic_vector(31 downto 0); mem_source : in mem_source_type; data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0); pause_out : out std_logic; address_next : out std_logic_vector(31 downto 2); byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0)); end component; component control port(opcode : in std_logic_vector(31 downto 0); intr_signal : in std_logic; rs_index : out std_logic_vector(5 downto 0); rt_index : out std_logic_vector(5 downto 0); rd_index : out std_logic_vector(5 downto 0); imm_out : out std_logic_vector(15 downto 0); alu_func : out alu_function_type; shift_func : out shift_function_type; mult_func : out mult_function_type; branch_func : out branch_function_type; a_source_out : out a_source_type; b_source_out : out b_source_type; c_source_out : out c_source_type; pc_source_out: out pc_source_type; mem_source_out:out mem_source_type; exception_out: out std_logic); end component; component reg_bank generic(memory_type : string := "XILINX_16X"); port(clk : in std_logic; reset_in : in std_logic; pause : in std_logic; rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); rd_index : in std_logic_vector(5 downto 0); reg_source_out : out std_logic_vector(31 downto 0); reg_target_out : out std_logic_vector(31 downto 0); reg_dest_new : in std_logic_vector(31 downto 0); intr_enable : out std_logic); end component; component bus_mux port(imm_in : in std_logic_vector(15 downto 0); reg_source : in std_logic_vector(31 downto 0); a_mux : in a_source_type; a_out : out std_logic_vector(31 downto 0); reg_target : in std_logic_vector(31 downto 0); b_mux : in b_source_type; b_out : out std_logic_vector(31 downto 0); c_bus : in std_logic_vector(31 downto 0); c_memory : in std_logic_vector(31 downto 0); c_pc : in std_logic_vector(31 downto 2); c_pc_plus4 : in std_logic_vector(31 downto 2); c_mux : in c_source_type; reg_dest_out : out std_logic_vector(31 downto 0); branch_func : in branch_function_type; take_branch : out std_logic); end component; component alu generic(alu_type : string := "DEFAULT"); port(a_in : in std_logic_vector(31 downto 0); b_in : in std_logic_vector(31 downto 0); alu_function : in alu_function_type; c_alu : out std_logic_vector(31 downto 0)); end component; component shifter generic(shifter_type : string := "DEFAULT" ); port(value : in std_logic_vector(31 downto 0); shift_amount : in std_logic_vector(4 downto 0); shift_func : in shift_function_type; c_shift : out std_logic_vector(31 downto 0)); end component; component mult generic(mult_type : string := "DEFAULT"); port(clk : in std_logic; reset_in : in std_logic; a, b : in std_logic_vector(31 downto 0); mult_func : in mult_function_type; c_mult : out std_logic_vector(31 downto 0); pause_out : out std_logic); end component; component pipeline port(clk : in std_logic; reset : in std_logic; a_bus : in std_logic_vector(31 downto 0); a_busD : out std_logic_vector(31 downto 0); b_bus : in std_logic_vector(31 downto 0); b_busD : out std_logic_vector(31 downto 0); alu_func : in alu_function_type; alu_funcD : out alu_function_type; shift_func : in shift_function_type; shift_funcD : out shift_function_type; mult_func : in mult_function_type; mult_funcD : out mult_function_type; reg_dest : in std_logic_vector(31 downto 0); reg_destD : out std_logic_vector(31 downto 0); rd_index : in std_logic_vector(5 downto 0); rd_indexD : out std_logic_vector(5 downto 0); rs_index : in std_logic_vector(5 downto 0); rt_index : in std_logic_vector(5 downto 0); pc_source : in pc_source_type; mem_source : in mem_source_type; a_source : in a_source_type; b_source : in b_source_type; c_source : in c_source_type; c_bus : in std_logic_vector(31 downto 0); pause_any : in std_logic; pause_pipeline : out std_logic); end component; component mlite_cpu generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_ mult_type : string := "DEFAULT"; shifter_type : string := "DEFAULT"; alu_type : string := "DEFAULT"; pipeline_stages : natural := 2); --2 or 3 port(clk : in std_logic; reset_in : in std_logic; intr_in : in std_logic; address_next : out std_logic_vector(31 downto 2); --for synch ram byte_we_next : out std_logic_vector(3 downto 0); address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_w : out std_logic_vector(31 downto 0); data_r : in std_logic_vector(31 downto 0); mem_pause : in std_logic); end component; component ram generic(memory_type : string := "DEFAULT"); port(clk : in std_logic; enable : in std_logic; write_byte_enable : in std_logic_vector(3 downto 0); address : in std_logic_vector(31 downto 2); data_write : in std_logic_vector(31 downto 0); data_read : out std_logic_vector(31 downto 0)); end component; --ram component uart generic(log_file : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; enable_read : in std_logic; enable_write : in std_logic; data_in : in std_logic_vector(7 downto 0); data_out : out std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; busy_write : out std_logic; data_avail : out std_logic); end component; --uart component eth_dma port(clk : in std_logic; --25 MHz reset : in std_logic; enable_eth : in std_logic; select_eth : in std_logic; rec_isr : out std_logic; send_isr : out std_logic; address : out std_logic_vector(31 downto 2); --to DDR byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); pause_in : in std_logic; mem_address : in std_logic_vector(31 downto 2); --from CPU mem_byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); pause_out : out std_logic; E_RX_CLK : in std_logic; --2.5 MHz receive E_RX_DV : in std_logic; --data valid E_RXD : in std_logic_vector(3 downto 0); --receive nibble E_TX_CLK : in std_logic; --2.5 MHz transmit E_TX_EN : out std_logic; --transmit enable E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble end component; --eth_dma component plasma generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM"; log_file : string := "UNUSED"; ethernet : std_logic := '0'); port(clk : in std_logic; reset : in std_logic; uart_write : out std_logic; uart_read : in std_logic; address : out std_logic_vector(31 downto 2); byte_we : out std_logic_vector(3 downto 0); data_write : out std_logic_vector(31 downto 0); data_read : in std_logic_vector(31 downto 0); mem_pause_in : in std_logic; gpio0_out : out std_logic_vector(31 downto 0); gpioA_in : in std_logic_vector(31 downto 0)); end component; --plasma component ddr_ctrl port(clk : in std_logic; clk_2x : in std_logic; reset_in : in std_logic; address : in std_logic_vector(25 downto 2); byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); data_r : out std_logic_vector(31 downto 0); active : in std_logic; pause : out std_logic; SD_CK_P : out std_logic; --clock_positive SD_CK_N : out std_logic; --clock_negative SD_CKE : out std_logic; --clock_enable SD_BA : out std_logic_vector(1 downto 0); --bank_address SD_A : out std_logic_vector(12 downto 0); --address(row or col) SD_CS : out std_logic; --chip_select SD_RAS : out std_logic; --row_address_strobe SD_CAS : out std_logic; --column_address_strobe SD_WE : out std_logic; --write_enable SD_DQ : inout std_logic_vector(15 downto 0); --data SD_UDM : out std_logic; --upper_byte_enable SD_UDQS : inout std_logic; --upper_data_strobe SD_LDM : out std_logic; --low_byte_enable SD_LDQS : inout std_logic); --low_data_strobe end component; --ddr end; --package mlite_pack package body mlite_pack is function bv_adder(a : in std_logic_vector; b : in std_logic_vector; do_add: in std_logic) return std_logic_vector is variable carry_in : std_logic; variable bb : std_logic_vector(a'length-1 downto 0); variable result : std_logic_vector(a'length downto 0); begin if do_add = '1' then bb := b; carry_in := '0'; else bb := not b; carry_in := '1'; end if; for index in 0 to a'length-1 loop result(index) := a(index) xor bb(index) xor carry_in; carry_in := (carry_in and (a(index) or bb(index))) or (a(index) and bb(index)); end loop; result(a'length) := carry_in xnor do_add; return result; end; --function function bv_negate(a : in std_logic_vector) return std_logic_vector is variable carry_in : std_logic; variable not_a : std_logic_vector(a'length-1 downto 0); variable result : std_logic_vector(a'length-1 downto 0); begin not_a := not a; carry_in := '1'; for index in a'reverse_range loop result(index) := not_a(index) xor carry_in; carry_in := carry_in and not_a(index); end loop; return result; end; --function function bv_increment(a : in std_logic_vector(31 downto 2) ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(31 downto 2); begin carry_in := '1'; for index in 2 to 31 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function function bv_inc(a : in std_logic_vector ) return std_logic_vector is variable carry_in : std_logic; variable result : std_logic_vector(a'length-1 downto 0); begin carry_in := '1'; for index in 0 to a'length-1 loop result(index) := a(index) xor carry_in; carry_in := a(index) and carry_in; end loop; return result; end; --function end; --package body @ 1.17 log @Latch address and byte_we in mem_ctrl.vhd @ text @a351 30 component ddr_ctrl port(clk : in std_logic; clk_2x : in std_logic; reset_in : in std_logic; address : in std_logic_vector(25 downto 2); byte_we : in std_logic_vector(3 downto 0); data_w : in std_logic_vector(31 downto 0); data_r : out std_logic_vector(31 downto 0); active : in std_logic; pause : out std_logic; SD_CK_P : out std_logic; --clock_positive SD_CK_N : out std_logic; --clock_negative SD_CKE : out std_logic; --clock_enable SD_BA : out std_logic_vector(1 downto 0); --bank_address SD_A : out std_logic_vector(12 downto 0); --address(row or col) SD_CS : out std_logic; --chip_select SD_RAS : out std_logic; --row_address_strobe SD_CAS : out std_logic; --column_address_strobe SD_WE : out std_logic; --write_enable SD_DQ : inout std_logic_vector(15 downto 0); --data SD_UDM : out std_logic; --upper_byte_enable SD_UDQS : inout std_logic; --upper_data_strobe SD_LDM : out std_logic; --low_byte_enable SD_LDQS : inout std_logic); --low_data_strobe end component; --ddr d366 27 d395 2 a396 1 log_file : string := "UNUSED"); d412 30 @ 1.16 log @Defined outputing PC as stage #0 @ text @a111 14 COMPONENT lpm_add_sub GENERIC ( lpm_width : NATURAL; lpm_direction : STRING := "UNUSED"; lpm_type : STRING; lpm_hint : STRING); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); add_sub : IN STD_LOGIC ; datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0)); END COMPONENT; -- For Altera d157 17 a173 40 component ramb4_s16_s16 port ( clka : in std_logic; rsta : in std_logic; addra : in std_logic_vector; dia : in std_logic_vector; ena : in std_logic; wea : in std_logic; doa : out std_logic_vector; clkb : in std_logic; rstb : in std_logic; addrb : in std_logic_vector; dib : in std_logic_vector; enb : in std_logic; web : in std_logic); end component; -- For Xilinx component reg_file_dp_ram port ( addra : IN std_logic_VECTOR(4 downto 0); addrb : IN std_logic_VECTOR(4 downto 0); clka : IN std_logic; clkb : IN std_logic; dinb : IN std_logic_VECTOR(31 downto 0); douta : OUT std_logic_VECTOR(31 downto 0); web : IN std_logic); end component; -- For Xilinx component reg_file_dp_ram_xc4000xla port ( A : IN std_logic_vector(4 DOWNTO 0); DI : IN std_logic_vector(31 DOWNTO 0); WR_EN : IN std_logic; WR_CLK : IN std_logic; DPRA : IN std_logic_vector(4 DOWNTO 0); SPO : OUT std_logic_vector(31 DOWNTO 0); DPO : OUT std_logic_vector(31 DOWNTO 0)); d202 8 a209 5 mem_address : out std_logic_vector(31 downto 2); mem_data_w : out std_logic_vector(31 downto 0); mem_data_r : in std_logic_vector(31 downto 0); mem_byte_we : out std_logic_vector(3 downto 0)); d332 8 a339 5 mem_address : out std_logic_vector(31 downto 0); mem_data_w : out std_logic_vector(31 downto 0); mem_data_r : in std_logic_vector(31 downto 0); mem_byte_we : out std_logic_vector(3 downto 0); mem_pause : in std_logic); d351 31 a381 1 d405 1 a407 1 write_byte_enable : out std_logic_vector(3 downto 0); @ 1.15 log @Implemented BREAK and SYSCALL opcodes @ text @d361 1 a361 1 pipeline_stages : natural := 3); --3 or 4 @ 1.14 log @Major changes -- updated to Plasma Version 3 @ text @d261 2 a262 1 mem_source_out:out mem_source_type); @ 1.13 log @Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. @ text @d88 1 d96 1 a96 1 constant MEM_READ16s : mem_source_type := "1010"; d99 1 a99 1 constant MEM_READ8s : mem_source_type := "1110"; d102 2 a103 7 function bv_to_integer(bv: in std_logic_vector) return integer; function bv_adder(a : in std_logic_vector(32 downto 0); b : in std_logic_vector(32 downto 0); do_add: in std_logic) return std_logic_vector; function bv_adder_lookahead( a : in std_logic_vector(32 downto 0); b : in std_logic_vector(32 downto 0); d107 3 a109 3 ) return std_logic_vector; function bv_inc6(a : in std_logic_vector ) return std_logic_vector; d191 8 a198 8 port ( addra : IN std_logic_VECTOR(4 downto 0); addrb : IN std_logic_VECTOR(4 downto 0); clka : IN std_logic; clkb : IN std_logic; dinb : IN std_logic_VECTOR(31 downto 0); douta : OUT std_logic_VECTOR(31 downto 0); web : IN std_logic); d203 8 a210 8 port ( A : IN std_logic_vector(4 DOWNTO 0); DI : IN std_logic_vector(31 DOWNTO 0); WR_EN : IN std_logic; WR_CLK : IN std_logic; DPRA : IN std_logic_vector(4 DOWNTO 0); SPO : OUT std_logic_vector(31 DOWNTO 0); DPO : OUT std_logic_vector(31 DOWNTO 0)); d214 10 a223 9 port(clk : in std_logic; reset_in : in std_logic; pc_new : in std_logic_vector(31 downto 2); take_branch : in std_logic; pause_in : in std_logic; opcode25_0 : in std_logic_vector(25 downto 0); pc_source : in pc_source_type; pc_out : out std_logic_vector(31 downto 0); pc_out_plus4 : out std_logic_vector(31 downto 0)); a226 1 generic(ACCURATE_TIMING : boolean := false); d231 1 a231 1 address_pc : in std_logic_vector(31 downto 0); d234 1 a234 1 address_data : in std_logic_vector(31 downto 0); d240 1 a240 1 mem_address : out std_logic_vector(31 downto 0); d243 1 a243 2 mem_byte_sel : out std_logic_vector(3 downto 0); mem_write : out std_logic); d265 1 a265 1 generic(memory_type : string := "TRI_PORT"); d290 2 a291 2 c_pc : in std_logic_vector(31 downto 0); c_pc_plus4 : in std_logic_vector(31 downto 0); d300 1 a300 2 generic(adder_type : string := "DEFAULT"; alu_type : string := "DEFAULT"); d308 1 a308 1 generic( shifter_type : string := "DEFAULT" ); d316 7 a322 10 generic ( adder_type : string := "DEFAULT"; mult_type : string := "DEFAULT"); port ( clk : in std_logic; reset_in : in std_logic; a, b : in std_logic_vector(31 downto 0); mult_func : in mult_function_type; c_mult : out std_logic_vector(31 downto 0); pause_out : out std_logic); d356 1 a356 1 generic(memory_type : string := "ALTERA"; d359 2 a360 1 pipeline_stages : natural := 3); d368 1 a368 2 mem_byte_sel: out std_logic_vector(3 downto 0); mem_write : out std_logic; d374 6 a379 6 port(clk : in std_logic; mem_byte_sel : in std_logic_vector(3 downto 0); mem_write : in std_logic; mem_address : in std_logic_vector(31 downto 0); mem_data_w : in std_logic_vector(31 downto 0); mem_data_r : out std_logic_vector(31 downto 0)); d384 10 a393 7 port(clk : in std_logic; reset : in std_logic; uart_sel : in std_logic; data : in std_logic_vector(7 downto 0); uart_read : in std_logic; uart_write : out std_logic; pause : out std_logic); d397 1 a397 1 generic(memory_type : string := "DEFAULT"; d399 13 a411 12 port(clk_in : in std_logic; reset_in : in std_logic; intr_in : in std_logic; uart_read : in std_logic; uart_write : out std_logic; mem_address_out : out std_logic_vector(31 downto 0); mem_data : out std_logic_vector(31 downto 0); mem_byte_sel_out : out std_logic_vector(3 downto 0); mem_write_out : out std_logic; mem_pause_in : in std_logic); d414 1 a414 16 component plasma_if generic(memory_type : string := "ALTERA"; log_file : string := "UNUSED"); port(clk_in : in std_logic; reset_n : in std_logic; uart_read : in std_logic; uart_write : out std_logic; address : out std_logic_vector(31 downto 0); data : out std_logic_vector(31 downto 0); we_n : out std_logic; oe_n : out std_logic; be_n : out std_logic_vector(3 downto 0); sram0_cs_n : out std_logic; sram1_cs_n : out std_logic); end component; --plasma_if a415 1 end; --package mlite_pack d419 2 a420 20 function bv_to_integer(bv: in std_logic_vector) return integer is variable result : integer; variable b : integer; begin result := 0; b := 0; for index in bv'range loop if bv(index) = '1' then b := 1; else b := 0; end if; result := result * 2 + b; end loop; return result; end; --function bv_to_integer function bv_adder(a : in std_logic_vector(32 downto 0); b : in std_logic_vector(32 downto 0); d423 2 a424 2 variable bb : std_logic_vector(32 downto 0); variable result : std_logic_vector(32 downto 0); a425 1 result := '0' & ZERO; d433 1 a433 1 for index in 0 to 32 loop d438 1 a438 47 return result; end; --function function bv_adder_lookahead( a : in std_logic_vector(32 downto 0); b : in std_logic_vector(32 downto 0); do_add: in std_logic) return std_logic_vector is variable carry : std_logic_vector(32 downto 0); variable p, g : std_logic_vector(32 downto 0); variable bb : std_logic_vector(32 downto 0); variable result : std_logic_vector(32 downto 0); variable i : natural; begin carry := '0' & ZERO; if do_add = '1' then bb := b; carry(0) := '0'; else bb := not b; carry(0) := '1'; end if; p := a or bb; --propogate g := a and bb; --generate for index in 0 to 7 loop i := index*4; carry(i+1) := g(i) or (p(i) and carry(i)); i := index*4+1; carry(i+1) := g(i) or (p(i) and g(i-1)) or ((p(i) and p(i-1)) and carry(i-1)); i := index*4+2; carry(i+1) := g(i) or (p(i) and g(i-1)) or (p(i) and p(i-1) and g(i-2)) or ((p(i) and p(i-1) and p(i-2)) and carry(i-2)); i := index*4+3; carry(i+1) := g(i) or (p(i) and g(i-1)) or (p(i) and p(i-1) and g(i-2)) or (p(i) and p(i-1) and p(i-2) and g(i-3)) or (((p(i) and p(i-1)) and (p(i-2) and p(i-3))) and carry(i-3)); end loop; result := (a xor bb) xor carry; d445 2 a446 2 variable not_a : std_logic_vector(31 downto 0); variable result : std_logic_vector(31 downto 0); a447 1 result := ZERO; a462 1 result := ZERO(31 downto 2); d472 2 a473 2 function bv_inc6(a : in std_logic_vector ) return std_logic_vector is d475 1 a475 1 variable result : std_logic_vector(5 downto 0); a476 1 result := "000000"; d478 1 a478 1 for index in 0 to 5 loop @ 1.12 log @Reset all registers, constants now upper case. @ text @d305 2 a306 2 generic(adder_type : string := "GENERIC"; alu_type : string := "GENERIC"); d314 1 a314 1 generic( shifter_type : string := "GENERIC" ); d323 2 a324 2 adder_type : string := "GENERIC"; mult_type : string := "GENERIC"); d366 2 a367 2 mult_type : string := "GENERIC"; shifter_type : string := "GENERIC"; d382 1 a382 1 generic(memory_type : string := "GENERIC"); d403 1 a403 1 generic(memory_type : string := "GENERIC"; @ 1.11 log @Fixed pc_source_type comment. @ text @a23 3 -- type alu_function_type is (alu_nothing, alu_add, alu_subtract, -- alu_less_than, alu_less_than_signed, -- alu_or, alu_and, alu_xor, alu_nor); d25 10 a34 13 constant alu_nothing : alu_function_type := "0000"; constant alu_add : alu_function_type := "0001"; constant alu_subtract : alu_function_type := "0010"; constant alu_less_than : alu_function_type := "0011"; constant alu_less_than_signed : alu_function_type := "0100"; constant alu_or : alu_function_type := "0101"; constant alu_and : alu_function_type := "0110"; constant alu_xor : alu_function_type := "0111"; constant alu_nor : alu_function_type := "1000"; -- type shift_function_type is ( -- shift_nothing, shift_left_unsigned, -- shift_right_signed, do_right_unsigned); d36 5 a40 8 constant shift_nothing : shift_function_type := "00"; constant shift_left_unsigned : shift_function_type := "01"; constant shift_right_signed : shift_function_type := "11"; constant shift_right_unsigned : shift_function_type := "10"; -- type mult_function_type is ( -- mult_nothing, mult_read_lo, mult_read_hi, mult_write_lo, -- mult_write_hi, mult_mult, mult_divide, mult_signed_divide); d42 9 a50 9 constant mult_nothing : mult_function_type := "0000"; constant mult_read_lo : mult_function_type := "0001"; constant mult_read_hi : mult_function_type := "0010"; constant mult_write_lo : mult_function_type := "0011"; constant mult_write_hi : mult_function_type := "0100"; constant mult_mult : mult_function_type := "0101"; constant mult_signed_mult : mult_function_type := "0110"; constant mult_divide : mult_function_type := "0111"; constant mult_signed_divide : mult_function_type := "1000"; a51 1 -- type a_source_type is (from_reg_source, from_imm10_6); d53 3 a55 3 constant a_from_reg_source : a_source_type := "00"; constant a_from_imm10_6 : a_source_type := "01"; constant a_from_pc : a_source_type := "10"; a56 1 -- type b_source_type is (from_reg_target, from_imm, from_signed_imm); d58 5 a62 8 constant b_from_reg_target : b_source_type := "00"; constant b_from_imm : b_source_type := "01"; constant b_from_signed_imm : b_source_type := "10"; constant b_from_immX4 : b_source_type := "11"; -- type c_source_type is (from_null, from_alu, from_shift, -- from_mult, from_memory, from_pc, from_imm_shift16, -- from_reg_source_nez, from_reg_source_eqz); d64 9 a72 9 constant c_from_null : c_source_type := "000"; constant c_from_alu : c_source_type := "001"; constant c_from_shift : c_source_type := "001"; --same as alu constant c_from_mult : c_source_type := "001"; --same as alu constant c_from_memory : c_source_type := "010"; constant c_from_pc : c_source_type := "011"; constant c_from_pc_plus4 : c_source_type := "100"; constant c_from_imm_shift16: c_source_type := "101"; constant c_from_reg_sourcen: c_source_type := "110"; a73 1 -- type pc_source_type is (from_inc4, from_opcode25_0, from_branch, from_lbranch); d75 4 a78 4 constant from_inc4 : pc_source_type := "00"; constant from_opcode25_0 : pc_source_type := "01"; constant from_branch : pc_source_type := "10"; constant from_lbranch : pc_source_type := "11"; d81 7 a87 7 constant branch_ltz : branch_function_type := "000"; constant branch_lez : branch_function_type := "001"; constant branch_eq : branch_function_type := "010"; constant branch_ne : branch_function_type := "011"; constant branch_gez : branch_function_type := "100"; constant branch_gtz : branch_function_type := "101"; constant branch_yes : branch_function_type := "110"; d91 9 a99 9 constant mem_fetch : mem_source_type := "0000"; constant mem_read32 : mem_source_type := "0100"; constant mem_write32 : mem_source_type := "0101"; constant mem_read16 : mem_source_type := "1000"; constant mem_read16s : mem_source_type := "1010"; constant mem_write16 : mem_source_type := "1001"; constant mem_read8 : mem_source_type := "1100"; constant mem_read8s : mem_source_type := "1110"; constant mem_write8 : mem_source_type := "1101"; d327 1 @ 1.10 log @Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. @ text @d88 1 a88 2 -- type pc_source_type is (from_inc4, from_inc8, from_reg_source, -- from_opcode25_0, from_branch, from_lbranch); @ 1.9 log @Simplify take_branch @ text @d209 24 d321 2 a322 1 generic(adder_type : string := "GENERIC"); d330 1 d338 9 a346 6 generic(adder_type : string := "GENERIC"); port(clk : in std_logic; a, b : in std_logic_vector(31 downto 0); mult_func : in mult_function_type; c_mult : out std_logic_vector(31 downto 0); pause_out : out std_logic); d381 2 @ 1.8 log @Removed unused alu_function_type entries @ text @a345 2 take_branch : in std_logic; take_branchD : out std_logic; @ 1.7 log @pipeline @ text @d25 1 a25 2 -- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal, -- alu_ltz, alu_lez, alu_eqz, alu_nez, alu_gez, alu_gtz, d27 10 a36 18 subtype alu_function_type is std_logic_vector(4 downto 0); constant alu_nothing : alu_function_type := "00000"; constant alu_add : alu_function_type := "00010"; constant alu_subtract : alu_function_type := "00011"; constant alu_less_than : alu_function_type := "00100"; constant alu_less_than_signed : alu_function_type := "00101"; constant alu_equal : alu_function_type := "00110"; constant alu_not_equal : alu_function_type := "00111"; constant alu_ltz : alu_function_type := "01000"; constant alu_lez : alu_function_type := "01001"; constant alu_eqz : alu_function_type := "01010"; constant alu_nez : alu_function_type := "01011"; constant alu_gez : alu_function_type := "01100"; constant alu_gtz : alu_function_type := "01101"; constant alu_or : alu_function_type := "01110"; constant alu_and : alu_function_type := "01111"; constant alu_xor : alu_function_type := "10001"; constant alu_nor : alu_function_type := "10010"; d134 4 a137 4 lpm_width : NATURAL; lpm_direction : STRING; lpm_type : STRING; lpm_hint : STRING); d139 4 a142 4 dataa : IN STD_LOGIC_VECTOR (32 DOWNTO 0); add_sub : IN STD_LOGIC ; datab : IN STD_LOGIC_VECTOR (32 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (32 DOWNTO 0)); d159 1 a159 1 wren : IN STD_LOGIC ; d161 4 a164 4 q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (4 DOWNTO 0)); d170 2 a171 2 LPM_WIDTH : natural; -- MUST be greater than 0 LPM_WIDTHAD : natural; -- MUST be greater than 0 d173 1 a173 1 LPM_INDATA : string := "REGISTERED"; d175 4 a178 4 LPM_OUTDATA : string := "REGISTERED"; LPM_FILE : string := "UNUSED"; LPM_TYPE : string := "LPM_RAM_DQ"; USE_EAB : string := "OFF"; d180 1 a180 1 LPM_HINT : string := "UNUSED"); d353 1 a353 1 generic(memory_type : string := "ALTERA"; a425 5 function add_1(a:integer) return integer is begin return a+1; end; --function d443 1 d467 1 d514 1 d530 1 d544 1 @ 1.6 log @updated LPM functions; mem_none->mem_fetch @ text @d231 1 d249 1 a249 2 mem_write : out std_logic; mem_pause : in std_logic); a254 1 pause_in : in std_logic; d274 1 d329 32 d362 2 a363 1 generic(memory_type : string := "ALTERA"); @ 1.5 log @Update prototypes @ text @d116 1 a116 1 constant mem_none : mem_source_type := "0000"; d177 21 a197 18 component lpm_ram_io GENERIC ( intended_device_family : string; lpm_width : natural; lpm_widthad : natural; lpm_indata : string := "REGISTERED"; lpm_address_control : string := "UNREGISTERED"; lpm_outdata : string := "UNREGISTERED"; lpm_file : string := "code.hex"; use_eab : string := "ON"; lpm_type : string := "LPM_RAM_DQ"); PORT ( outenab : in std_logic; address : in std_logic_vector(lpm_widthad-1 downto 0); inclock : in std_logic; we : in std_logic; dio : inout std_logic_vector(lpm_width-1 downto 0)); end component; --lpm_ram_io d349 2 a350 1 mem_data : inout std_logic_vector(31 downto 0)); d375 1 a375 1 mem_data : inout std_logic_vector(31 downto 0); d380 17 @ 1.4 log @Altera @ text @d340 2 a341 3 -- For test bench (not synthesizable) component ram generic(load_file_name : string); d345 2 a346 3 mem_address : in std_logic_vector; mem_data_w : in std_logic_vector(31 downto 0); mem_data_r : out std_logic_vector(31 downto 0)); d350 8 a357 8 generic(save_file_name : string := "UNUSED"); port(clk : in std_logic; reset : in std_logic; uart_sel : in std_logic; data : in std_logic_vector(7 downto 0); read_pin : in std_logic; write_pin : out std_logic; pause : out std_logic); d359 17 @ 1.3 log @Fixed signed 64-bit multiply @ text @d129 1 a129 1 do_sub: in std_logic) return std_logic_vector; d133 1 a133 1 do_sub: in std_logic) return std_logic_vector; d139 223 d390 1 a390 1 do_sub: in std_logic) return std_logic_vector is d395 2 a396 2 result := "000000000000000000000000000000000"; if do_sub = '0' then d414 1 a414 1 do_sub: in std_logic) return std_logic_vector is d421 2 a422 2 carry := "000000000000000000000000000000000"; if do_sub = '0' then d477 1 a477 1 result := "000000000000000000000000000000"; @ 1.2 log @Renamed M-lite to Plasma @ text @d59 10 a68 9 subtype mult_function_type is std_logic_vector(2 downto 0); constant mult_nothing : mult_function_type := "000"; constant mult_read_lo : mult_function_type := "001"; constant mult_read_hi : mult_function_type := "010"; constant mult_write_lo : mult_function_type := "011"; constant mult_write_hi : mult_function_type := "100"; constant mult_mult : mult_function_type := "101"; constant mult_divide : mult_function_type := "110"; constant mult_signed_divide : mult_function_type := "111"; @ 1.1 log @Changed name to M-lite to avoid trademark issues. @ text @d2 1 a2 1 -- TITLE: M-lite Misc. Package d6 1 a6 1 -- PROJECT: M-lite CPU core d10 1 a10 1 -- Data types, constants, and add functions needed for the M-lite CPU. @