head 1.7; access; symbols bg2_23:1.7 bg2_22:1.7 bg2_21:1.7 bg2_20:1.7 bg2_16:1.7 bg2_15:1.7 bg2_12:1.7 bg2_07:1.7 isorc2008_submission:1.6 handbook_alpha_edition:1.6 jtres2007_submission:1.6 bg1_07:1.6 bg1_06:1.4 bg1_05:1.4 TAL_101:1.4 TAL_100:1.4 jtres_submission:1.4 wises06_submission:1.4 lctes2006_submission:1.4 rtgc_isorc2006:1.4.0.4 isorc2006:1.4.0.2 rtgc_paper:1.4 bg1_00:1.4 nohandle:1.4 thesis:1.4 arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.7 date 2008.02.23.23.18.43; author martin; state Exp; branches; next 1.6; commitid b7347c0a9b84567; 1.6 date 2006.12.29.14.13.05; author martin; state Exp; branches; next 1.5; commitid 2271459522704567; 1.5 date 2006.12.29.13.48.04; author martin; state Exp; branches; next 1.4; commitid 2db45951c914567; 1.4 date 2005.02.05.17.02.48; author martin; state Exp; branches; next 1.3; 1.3 date 2004.09.13.14.38.09; author martin; state Exp; branches; next 1.2; 1.2 date 2004.04.07.18.32.08; author martin; state Exp; branches; next 1.1; 1.1 date 2004.02.19.13.24.52; author martin; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2004.02.19.13.24.52; author martin; state Exp; branches; next ; desc @@ 1.7 log @JOP goes GPL @ text @-- -- -- This file is a part of JOP, the Java Optimized Processor -- -- Copyright (C) 2001-2008, Martin Schoeberl (martin@@jopdesign.com) -- -- This program is free software: you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see . -- -- -- fetch.vhd -- -- jop instrcution fetch and branch -- -- -- resources on ACEX1K30-3 -- -- 132 LCs, max ca. 50 MHz -- -- todo: -- 5 stage pipeline (jtbl/rom) -- relativ address for jp, br -- load pc instead of addres mux befor rom! -- -- 2001-07-04 first version -- 2001-07-18 component pc_inc in own file for Xilinx -- 2001-10-24 added 2 delays for br address (address is now in br opcode!) -- 2001-10-28 ldjpc, stjpc -- 2001-10-31 stbc (write content of jbc) -- 2001-11-13 added jtbl (jtbl and rom in one pipline stage!) -- 2001-11-14 change jbc to 1024 bytes -- 2001-11-16 split to fetch and bcfetch -- 2001-12-06 ir from decode to rom, (one brdly removed) -- mux befor rom removed, unregistered jfetch conrols imput to -- pc, jpaddr unregistered! -- 2001-12-07 branch relativ -- 2001-12-08 use table for branch offsets -- 2001-12-08 instruction set changed to 8 bit, pc to 10 bits -- 2002-12-02 wait instruction for memory -- 2003-08-15 move bcfetch to core -- 2004-04-06 nxt and opd are in rom. rom address from jpc_mux and with -- positiv edge rdaddr. unregistered output in rom. -- 2004-10-08 moved bsy/pcwait from decode to fetch -- -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity fetch is generic ( pc_width : integer; -- address bits of internal instruction rom i_width : integer -- instruction width ); port ( clk, reset : in std_logic; nxt, opd : out std_logic; -- jfetch and jopdfetch from table br : in std_logic; bsy : in std_logic; -- direct from the memory module jpaddr : in std_logic_vector(pc_width-1 downto 0); dout : out std_logic_vector(i_width-1 downto 0) -- internal instruction (rom) ); end fetch; architecture rtl of fetch is -- -- rom component (use technology specific vhdl-file (arom/xrom)) -- or generic rom.vhd -- -- rom registered address, unregisterd out -- component rom is generic (width : integer; addr_width : integer); port ( clk : in std_logic; address : in std_logic_vector(pc_width-1 downto 0); q : out std_logic_vector(i_width+1 downto 0) ); end component; -- -- offsets for relativ branches. -- component offtbl is port ( idx : in std_logic_vector(4 downto 0); q : out std_logic_vector(pc_width-1 downto 0) ); end component; signal pc_mux : std_logic_vector(pc_width-1 downto 0); signal pc_inc : std_logic_vector(pc_width-1 downto 0); signal pc : std_logic_vector(pc_width-1 downto 0); signal brdly : std_logic_vector(pc_width-1 downto 0); signal off : std_logic_vector(pc_width-1 downto 0); signal jfetch : std_logic; -- fetch next byte code as opcode signal jopdfetch : std_logic; -- fetch next byte code as operand signal rom_data : std_logic_vector(i_width+1 downto 0); -- output from ROM signal ir : std_logic_vector(i_width-1 downto 0); -- instruction register signal pcwait : std_logic; begin -- -- pc_mux is 1 during reset! -- => first instruction from ROM gets NEVER executed. -- cmp_rom: rom generic map (i_width+2, pc_width) port map(clk, pc_mux, rom_data); jfetch <= rom_data(9); jopdfetch <= rom_data(8); cmp_off: offtbl port map(ir(4 downto 0), off); dout <= ir; nxt <= jfetch; opd <= jopdfetch; process(clk) begin if rising_edge(clk) then -- we don't need a reset ir <= rom_data(7 downto 0); -- better read (second) instruction from room pcwait <= '0'; -- decode wait instruction from unregistered rom if (rom_data(7 downto 0)="10000001") then -- wait instuction pcwait <= '1'; end if; end if; end process; process(clk, reset, pc, off) begin if (reset='1') then pc <= std_logic_vector(to_unsigned(0, pc_width)); brdly <= std_logic_vector(to_unsigned(0, pc_width)); elsif rising_edge(clk) then brdly <= std_logic_vector(unsigned(pc) + unsigned(off)); pc <= pc_mux; end if; end process; -- bsy is too late to register pcwait and bsy pc_inc <= std_logic_vector(to_unsigned(0, pc_width-1)) & not (pcwait and bsy); process(jfetch, br, jpaddr, brdly, pc, pc_inc) begin if (jfetch='1') then pc_mux <= jpaddr; else if (br='1') then pc_mux <= brdly; else pc_mux <= std_logic_vector(unsigned(pc) + unsigned(pc_inc)); end if; end if; end process; end rtl; @ 1.6 log @use pc_width for pc_inc value @ text @d2 21 @ 1.5 log @removed component declaration of bcfetbl @ text @d146 1 a146 1 pc_inc <= "000000000" & not (pcwait and bsy); @ 1.4 log @Thesis version @ text @d46 2 a47 2 pc_width : integer := 10; -- address bits of internal instruction rom i_width : integer := 8 -- instruction width a89 11 -- -- table to generate jfetch and jopdfetch -- generated from Jopa.java -- component bcfetbl is port ( addr : in std_logic_vector(pc_width-1 downto 0); nxt, opd : out std_logic ); end component; a114 3 -- not used anymore -- cmp_bft: bcfetbl port map(pc, jfetch, jopdfetch); @ 1.3 log @bytecode load in hardware. @ text @d34 1 d55 1 a55 1 pcwait : in std_logic; d113 1 a136 1 d139 5 a144 1 a152 1 a153 1 a155 1 a156 1 d159 2 a160 1 pc_inc <= "000000000" & not pcwait; a162 1 a163 1 a172 1 @ 1.2 log @Tuning of bytecode and microcode fetch. 10 bits ROM instead of 8 bits plus bcftbl-table. Jopa generates an additional generic VHDL file for the microinstruction ROM (rom.vhd). @ text @d160 1 a160 1 process(jfetch, br, jpaddr, brdly, pc) @ 1.1 log @Initial revision @ text @d4 2 a5 1 -- jbc and instr fetch d32 2 a44 1 jpc_width : integer := 10; -- address bits of java byte code pc d65 1 d67 1 a67 1 -- rom unregistered address (or registered on negativ clock edge), registerd out (=ir) d76 1 a76 1 q : out std_logic_vector(i_width-1 downto 0) d100 2 a102 1 signal pcin : std_logic_vector(pc_width-1 downto 0); d110 1 d115 1 d117 2 a118 1 -- jop instrcution fetch and branch d120 3 d124 2 a125 2 cmp_rom: rom generic map (i_width, pc_width) port map(clk, pc, ir); cmp_bft: bcfetbl port map(pc, jfetch, jopdfetch); d133 8 d152 1 a152 1 pc <= pcin; d158 1 d160 1 a160 1 process(jfetch, br, pcwait, jpaddr, brdly, pc) d165 7 a171 7 pcin <= jpaddr; elsif (br='1') then pcin <= brdly; elsif (pcwait='1') then pcin <= pc; else pcin <= std_logic_vector(unsigned(pc) + 1); @ 1.1.1.1 log @initial cvs import. @ text @@