head 1.1; branch 1.1.1; access ; symbols vlsi:1.1.1.1 marta:1.1.1; locks ; strict; comment @# @; 1.1 date 2002.02.09.13.46.55; author marta; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2002.02.09.13.46.55; author marta; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @-- VHDL data flow description generated from `count4x` -- date : Thu Aug 2 08:55:34 2001 -- Entity Declaration ENTITY count4x IS PORT ( clk : in BIT; -- clk rst : in BIT; -- rst q : out bit_vector(3 DOWNTO 0) ; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END count4x; -- Architecture Declaration ARCHITECTURE VBE OF count4x IS SIGNAL current_state : REG_VECTOR(3 DOWNTO 0) REGISTER; -- current_state SIGNAL current_state_s15 : BIT; -- current_state_s15 SIGNAL next_state_s15 : BIT; -- next_state_s15 SIGNAL current_state_s14 : BIT; -- current_state_s14 SIGNAL next_state_s14 : BIT; -- next_state_s14 SIGNAL current_state_s13 : BIT; -- current_state_s13 SIGNAL next_state_s13 : BIT; -- next_state_s13 SIGNAL current_state_s12 : BIT; -- current_state_s12 SIGNAL next_state_s12 : BIT; -- next_state_s12 SIGNAL current_state_s11 : BIT; -- current_state_s11 SIGNAL next_state_s11 : BIT; -- next_state_s11 SIGNAL current_state_s10 : BIT; -- current_state_s10 SIGNAL next_state_s10 : BIT; -- next_state_s10 SIGNAL current_state_s9 : BIT; -- current_state_s9 SIGNAL next_state_s9 : BIT; -- next_state_s9 SIGNAL current_state_s8 : BIT; -- current_state_s8 SIGNAL next_state_s8 : BIT; -- next_state_s8 SIGNAL current_state_s7 : BIT; -- current_state_s7 SIGNAL next_state_s7 : BIT; -- next_state_s7 SIGNAL current_state_s6 : BIT; -- current_state_s6 SIGNAL next_state_s6 : BIT; -- next_state_s6 SIGNAL current_state_s5 : BIT; -- current_state_s5 SIGNAL next_state_s5 : BIT; -- next_state_s5 SIGNAL current_state_s4 : BIT; -- current_state_s4 SIGNAL next_state_s4 : BIT; -- next_state_s4 SIGNAL current_state_s3 : BIT; -- current_state_s3 SIGNAL next_state_s3 : BIT; -- next_state_s3 SIGNAL current_state_s2 : BIT; -- current_state_s2 SIGNAL next_state_s2 : BIT; -- next_state_s2 SIGNAL current_state_s1 : BIT; -- current_state_s1 SIGNAL next_state_s1 : BIT; -- next_state_s1 SIGNAL current_state_s0 : BIT; -- current_state_s0 SIGNAL next_state_s0 : BIT; -- next_state_s0 SIGNAL next_state : BIT_VECTOR(3 DOWNTO 0); -- next_state BEGIN next_state(0) <= (next_state_s0 OR next_state_s1 OR next_state_s3 OR next_state_s4 OR next_state_s6 OR next_state_s8 OR next_state_s12 OR next_state_s14); next_state(1) <= (next_state_s0 OR next_state_s1 OR next_state_s2 OR next_state_s4 OR next_state_s5 OR next_state_s9 OR next_state_s12 OR next_state_s13); next_state(2) <= (next_state_s0 OR next_state_s1 OR next_state_s2 OR next_state_s3 OR next_state_s5 OR next_state_s8 OR next_state_s10 OR next_state_s11); next_state(3) <= (next_state_s1 OR next_state_s2 OR next_state_s4 OR next_state_s6 OR next_state_s7 OR next_state_s8 OR next_state_s9 OR next_state_s10); next_state_s0 <= current_state_s15; current_state_s0 <= (NOT(current_state(3)) AND current_state(2) AND current_state(1) AND current_state(0)); next_state_s1 <= current_state_s0; current_state_s1 <= (current_state(3) AND current_state(2) AND current_state(1) AND current_state(0)); next_state_s2 <= current_state_s1; current_state_s2 <= (current_state(3) AND current_state(2) AND current_state(1) AND NOT(current_state(0))); next_state_s3 <= current_state_s2; current_state_s3 <= (NOT(current_state(3)) AND current_state(2) AND NOT(current_state(1)) AND current_state(0)); next_state_s4 <= current_state_s3; current_state_s4 <= (current_state(3) AND NOT(current_state(2)) AND current_state(1) AND current_state(0)); next_state_s5 <= current_state_s4; current_state_s5 <= (NOT(current_state(3)) AND current_state(2) AND current_state(1) AND NOT(current_state(0))); next_state_s6 <= current_state_s5; current_state_s6 <= (current_state(3) AND NOT(current_state(2)) AND NOT(current_state(1)) AND current_state(0)); next_state_s7 <= current_state_s6; current_state_s7 <= (current_state(3) AND NOT(current_state(2)) AND NOT(current_state(1)) AND NOT(current_state(0))); next_state_s8 <= current_state_s7; current_state_s8 <= (current_state(3) AND current_state(2) AND NOT( current_state(1)) AND current_state(0)); next_state_s9 <= current_state_s8; current_state_s9 <= (current_state(3) AND NOT(current_state(2)) AND current_state(1) AND NOT(current_state(0))); next_state_s10 <= current_state_s9; current_state_s10 <= (current_state(3) AND current_state(2) AND NOT( current_state(1)) AND NOT(current_state(0))); next_state_s11 <= current_state_s10; current_state_s11 <= (NOT(current_state(3)) AND current_state(2) AND NOT(current_state(1)) AND NOT(current_state(0))); next_state_s12 <= current_state_s11; current_state_s12 <= (NOT(current_state(3)) AND NOT(current_state(2)) AND current_state(1) AND current_state(0)); next_state_s13 <= current_state_s12; current_state_s13 <= (NOT(current_state(3)) AND NOT(current_state(2)) AND current_state(1) AND NOT(current_state(0))); next_state_s14 <= current_state_s13; current_state_s14 <= (NOT(current_state(3)) AND NOT(current_state(2)) AND NOT(current_state(1)) AND current_state(0)); next_state_s15 <= current_state_s14; current_state_s15 <= (NOT(current_state(3)) AND NOT(current_state(2)) AND NOT(current_state(1)) AND NOT(current_state(0))); label0 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1') BEGIN current_state(0) <= GUARDED (next_state(0) OR rst); END BLOCK label0; label1 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1') BEGIN current_state(1) <= GUARDED (next_state(1) OR rst); END BLOCK label1; label2 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1') BEGIN current_state(2) <= GUARDED (next_state(2) OR rst); END BLOCK label2; label3 : BLOCK ((NOT((clk'STABLE)) AND clk) = '1') BEGIN current_state(3) <= GUARDED (next_state(3) AND NOT(rst)); END BLOCK label3; q(0) <= ((current_state_s1 AND NOT(rst)) OR ( current_state_s3 AND NOT(rst)) OR (current_state_s5 AND NOT(rst)) OR (current_state_s7 AND NOT(rst)) OR ( current_state_s9 AND NOT(rst)) OR (current_state_s11 AND NOT(rst) ) OR (current_state_s13 AND NOT(rst)) OR ( current_state_s15 AND NOT(rst))); q(1) <= ((current_state_s2 AND NOT(rst)) OR ( current_state_s3 AND NOT(rst)) OR (current_state_s6 AND NOT(rst)) OR (current_state_s7 AND NOT(rst)) OR ( current_state_s10 AND NOT(rst)) OR (current_state_s11 AND NOT(rst) ) OR (current_state_s14 AND NOT(rst)) OR ( current_state_s15 AND NOT(rst))); q(2) <= ((current_state_s4 AND NOT(rst)) OR ( current_state_s5 AND NOT(rst)) OR (current_state_s6 AND NOT(rst)) OR (current_state_s7 AND NOT(rst)) OR ( current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst) ) OR (current_state_s14 AND NOT(rst)) OR ( current_state_s15 AND NOT(rst))); q(3) <= ((current_state_s8 AND NOT(rst)) OR ( current_state_s9 AND NOT(rst)) OR (current_state_s10 AND NOT(rst) ) OR (current_state_s11 AND NOT(rst)) OR ( current_state_s12 AND NOT(rst)) OR (current_state_s13 AND NOT(rst) ) OR (current_state_s14 AND NOT(rst)) OR ( current_state_s15 AND NOT(rst))); END; @ 1.1.1.1 log @no message @ text @@