head	1.1;
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	arelease:1.1.1.2
	avendor:1.1.1;
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1.1
date	2008.06.06.09.19.30;	author hmanske;	state Exp;
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	1.1.1.1;
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commitid	58624849010f4567;

1.1.1.1
date	2008.06.06.09.19.30;	author hmanske;	state Exp;
branches;
next	1.1.1.2;
commitid	58624849010f4567;

1.1.1.2
date	2008.06.06.10.27.06;	author hmanske;	state Exp;
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commitid	7895484910e74567;


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1.1
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@Initial revision
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@------------------------------------------------------------------
-- PROJECT:     clvp (configurable lightweight vector processor)
--
-- ENTITY:      multiplexer2
--
-- PURPOSE:     multiplexer, two inputs
--              one output
--
-- AUTHOR:      harald manske, haraldmanske@@gmx.de
--
-- VERSION:     1.0
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity multiplexer2 is
    generic (
        w : positive -- word width
    );
    port (   
        selector:   in std_logic;
        data_in_0:  in std_logic_vector(w-1 downto 0);
        data_in_1:  in std_logic_vector(w-1 downto 0);
        data_out:   out std_logic_vector(w-1 downto 0)
    );
end multiplexer2;

architecture rtl of multiplexer2 is   
begin
   data_out <=  data_in_0 when selector = '0' else
                data_in_1;
end rtl;

@


1.1.1.1
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1.1.1.2
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@d2 1
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-- PROJECT:      HiCoVec (highly configurable vector processor)
@