head	1.3;
access;
symbols;
locks; strict;
comment	@# @;


1.3
date	2001.10.22.20.21.35;	author khatib;	state Exp;
branches;
next	1.2;

1.2
date	2001.05.28.19.14.22;	author khatib;	state Exp;
branches;
next	1.1;

1.1
date	2001.01.26.20.54.09;	author khatib;	state Exp;
branches;
next	;


desc
@@


1.3
log
@Backend bug fixed
@
text
@-------------------------------------------------------------------------------
-- Title      :  Zero Insertion
-- Project    :  HDLC controller
-------------------------------------------------------------------------------
-- File        : zero_ins.vhd
-- Author      : Jamil Khatib  (khatib@@ieee.org)
-- Organization: OpenIPCore Project
-- Created     : 2001/01/12
-- Last update:2001/10/20
-- Platform    : 
-- Simulators  : Modelsim 5.3XE/Windows98
-- Synthesizers: 
-- Target      : 
-- Dependency  : ieee.std_logic_1164
--
-------------------------------------------------------------------------------
-- Description:  Zero Insertion
-------------------------------------------------------------------------------
-- Copyright (c) 2000 Jamil Khatib
-- 
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-- You can check the draft license at
-- http://www.opencores.org/OIPC/license.shtml

-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   1
-- Version         :   0.1
-- Date            :   12 Jan 2001
-- Modifier        :   Jamil Khatib (khatib@@ieee.org)
-- Desccription    :   Created
-------------------------------------------------------------------------------
-- Revisions  :
-- Revision Number :   2
-- Version         :   0.2
-- Date            :   27 May 2001
-- Modifier        :   Jamil Khatib (khatib@@ieee.org)
-- Desccription    :   Tx zero insertion bug fixed
--                     Zero is inserted after 5 sequence of 1's insted of 6 1's
-------------------------------------------------------------------------------
-- $Log: zero_ins.vhd,v $
-- Revision 1.2  2001/05/28 19:14:22  khatib
-- TX zero insertion bug fixed
--
-------------------------------------------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY ZeroIns_ent IS

  PORT (
    TxClk         : IN  STD_LOGIC;      -- Tx clock
    rst_n         : IN  STD_LOGIC;      -- system reset
    enable        : IN  STD_LOGIC;      -- enable (Driven by controller)
    inProgress    : OUT STD_LOGIC;      -- Data in progress
    BackendEnable : IN  STD_LOGIC;      -- Backend Enable
    -- backend interface
    abortedTrans  : OUT STD_LOGIC;      -- aborted Transmission
    ValidFrame    : IN  STD_LOGIC;      -- Valid Frame signal
    Writebyte     : IN  STD_LOGIC;      -- Back end write byte
    rdy           : OUT STD_LOGIC;      -- data ready
    TXD           : OUT STD_LOGIC;      -- TX serial data
    Data          : IN  STD_LOGIC_VECTOR(7 DOWNTO 0));  -- TX data bus

END ZeroIns_ent;
-------------------------------------------------------------------------------
ARCHITECTURE zero_ins_beh OF ZeroIns_ent IS

  SIGNAL data_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);  -- Data register (used as
                                        -- internal buffer)
  SIGNAL flag     : STD_LOGIC;          -- control signal between processes
  SIGNAL delay_TX : STD_LOGIC;          -- Delayed output

BEGIN  -- zero_ins_beh


  -- purpose: Parallel to Serial
  -- type   : sequential
  -- inputs : TxClk, rst_n
  -- outputs: 
  P2S_proc                : PROCESS (TxClk, rst_n)
    VARIABLE tmp_reg      : STD_LOGIC_VECTOR(15 DOWNTO 0);  -- Temp Shift register
    VARIABLE counter      : INTEGER RANGE 0 TO 8;  -- Counter
    VARIABLE OnesDetected : STD_LOGIC;  -- 6 ones detected

  BEGIN  -- process P2S_proc
    IF rst_n = '0' THEN                 -- asynchronous reset (active low)

      tmp_reg      := (OTHERS => '0');
      Counter      := 0;
      flag         <= '1';
      OnesDetected := '0';
      TXD          <= '1';
      delay_TX     <= '1';
      inProgress   <= '0';

    ELSIF TxClk'event AND TxClk = '1' THEN  -- rising clock edge
      IF enable = '1' THEN

        OnesDetected := tmp_reg(0) AND tmp_reg(1) AND tmp_reg(2) AND tmp_reg(3) AND tmp_reg(4);

        delay_TX <= tmp_reg(0);
        TXD      <= delay_TX;

        IF OnesDetected = '1' THEN
          -- Zero insertion 
          tmp_reg(4 DOWNTO 0) := '0' & tmp_reg(4 DOWNTO 1);

        ELSE
          -- Total Shift
          tmp_reg(15 DOWNTO 0) := '0' & tmp_reg(15 DOWNTO 1);

          Counter := Counter +1;

        END IF;  -- ones detected

        IF counter = 8 THEN

          counter    := 0;
          flag       <= '1';
          inProgress <= '0';

          tmp_reg(15 DOWNTO 8) := data_reg;
        ELSE
          inProgress           <= '1';
          flag                 <= '0';
        END IF;  -- counter
      END IF;  -- enable
    END IF;  -- clk
  END PROCESS P2S_proc;
-------------------------------------------------------------------------------

  -- purpose: Backend Interface
  -- type   : sequential
  -- inputs : TxClk, rst_n
  -- outputs:   
  Backend_proc     : PROCESS (TxClk, rst_n)
    VARIABLE state : STD_LOGIC;         -- Backend state

  BEGIN  -- process Backend_proc
    IF rst_n = '0' THEN                     -- asynchronous reset (active low)
      state              := '0';
      data_reg           <= (OTHERS => '0');
      rdy                <= '0';
      abortedTrans       <= '0';
    ELSIF TxClk'event AND TxClk = '1' THEN  -- rising clock edge
      IF enable = '1' THEN
        IF BackendEnable = '1' THEN
          CASE state IS
            WHEN '0'                =>      -- wait for reading the register
              IF flag = '1' THEN            -- Register has been read
                state    := '1';
                rdy      <= '1';
                data_reg <= "00000000";     -- set register to known pattern to
                                            -- avoid invalid read (upon valid
                                            -- read this value will be overwritten)
              END IF;

            WHEN '1' =>
              IF WriteByte = '1' THEN
                state        := '0';
                rdy          <= '0';
                data_reg     <= Data;
              ELSIF flag = '1' THEN     -- Another flag but without read
                state        := '0';
                rdy          <= '0';
                data_reg     <= "00000000";
                abortedTrans <= '1';
              END IF;

            WHEN OTHERS => NULL;
          END CASE;

        ELSE
          rdy          <= '0';
          state        := '0';
          abortedTrans <= '0';
        END IF;  -- Backend enable

      END IF;  -- enable
    END IF;  -- Txclk
  END PROCESS Backend_proc;


END zero_ins_beh;
@


1.2
log
@TX zero insertion bug fixed
@
text
@d9 1
a9 1
-- Last update: 2001/05/27
d42 4
a45 1
-- $Log$
d48 2
a49 2
library ieee;
use ieee.std_logic_1164.all;
d51 1
a51 1
entity ZeroIns_ent is
d53 6
a58 6
  port (
    TxClk         : in  std_logic;      -- Tx clock
    rst_n         : in  std_logic;      -- system reset
    enable        : in  std_logic;      -- enable (Driven by controller)
    inProgress    : out std_logic;      -- Data in progress
    BackendEnable : in  std_logic;      -- Backend Enable
d60 6
a65 6
    abortedTrans  : out std_logic;      -- aborted Transmission
    ValidFrame    : in  std_logic;      -- Valid Frame signal
    Writebyte     : in  std_logic;      -- Back end write byte
    rdy           : out std_logic;      -- data ready
    TXD           : out std_logic;      -- TX serial data
    Data          : in  std_logic_vector(7 downto 0));  -- TX data bus
d67 1
a67 1
end ZeroIns_ent;
d69 1
a69 1
architecture zero_ins_beh of ZeroIns_ent is
d71 1
a71 1
  signal data_reg : std_logic_vector(7 downto 0);  -- Data register (used as
d73 2
a74 2
  signal flag     : std_logic;          -- control signal between processes
  signal delay_TX : std_logic;          -- Delayed output
d76 1
a76 1
begin  -- zero_ins_beh
d83 4
a86 4
  P2S_proc                : process (TxClk, rst_n)
    variable tmp_reg      : std_logic_vector(15 downto 0);  -- Temp Shift register
    variable counter      : integer range 0 to 8;  -- Counter
    variable OnesDetected : std_logic;  -- 6 ones detected
d88 2
a89 2
  begin  -- process P2S_proc
    if rst_n = '0' then                 -- asynchronous reset (active low)
d91 1
a91 1
      tmp_reg      := (others => '0');
d99 2
a100 2
    elsif TxClk'event and TxClk = '1' then  -- rising clock edge
      if enable = '1' then
d102 1
a102 1
        OnesDetected := tmp_reg(0) and tmp_reg(1) and tmp_reg(2) and tmp_reg(3) and tmp_reg(4);
d107 1
a107 1
        if OnesDetected = '1' then
d109 1
a109 1
          tmp_reg(4 downto 0) := '0' & tmp_reg(4 downto 1);
d111 1
a111 1
        else
d113 1
a113 1
          tmp_reg(15 downto 0) := '0' & tmp_reg(15 downto 1);
d117 1
a117 1
        end if;  -- ones detected
d119 1
a119 1
        if counter = 8 then
d125 2
a126 2
          tmp_reg(15 downto 8) := data_reg;
        else
d129 4
a132 4
        end if;  -- counter
      end if;  -- enable
    end if;  -- clk
  end process P2S_proc;
d135 1
a135 1
  -- purpose: Baclend Interface
d139 46
a184 2
  Backend_proc     : process (TxClk, rst_n)
    variable state : std_logic;         -- Backend state
a185 44
  begin  -- process Backend_proc
    if rst_n = '0' then                     -- asynchronous reset (active low)
      state        := '0';
      data_reg     <= (others => '0');
      rdy          <= '0';
      abortedTrans <= '0';
    elsif TxClk'event and TxClk = '1' then  -- rising clock edge
      if enable = '1' then
        if BackendEnable = '1' then
          if ValidFrame = '1' then

            case state is
              when '0' =>                  -- wait for reading the register
                if flag = '1' then         -- Register has been read
                  state    := '1';
                  rdy      <= '1';
                  data_reg <= "00000000";  -- set register to known pattern to
                                           -- avoid invalid read (upon valid
                                           -- read this value will be overwritten)
                end if;

              when '1' =>
                if WriteByte = '1' then
                  state    := '0';
                  rdy      <= '0';
                  data_reg <= Data;
                elsif flag = '1' then   -- Another flag but without read
                  state        := '0';
                  rdy          <= '0';
                  data_reg     <= "00000000";
                  abortedTrans <= '1';
                end if;

              when others           => null;
            end case;
          else
            abortedTrans <= '0';
          end if;  -- ValidFrame
        else
          data_reg       <= (others => '0');
        end if;  -- Backend enable
      end if;  -- enable
    end if;  -- Txclk
  end process Backend_proc;
d187 1
a187 2
  
end zero_ins_beh;
@


1.1
log
@Initial release (TX)
@
text
@d9 1
a9 1
-- Last update: 2001/01/26
d33 10
a42 1
--
d99 1
a99 1
        OnesDetected := tmp_reg(0) and tmp_reg(1) and tmp_reg(2) and tmp_reg(3) and tmp_reg(4) and tmp_reg(5);
@