head	1.4;
access;
symbols
	rel_15:1.4
	rel_13:1.4
	rel_12:1.3
	rel_11:1.2
	rel_10:1.1;
locks; strict;
comment	@# @;


1.4
date	2003.12.17.13.00.52;	author gorand;	state Exp;
branches;
next	1.3;

1.3
date	2003.12.09.11.14.39;	author gorand;	state Exp;
branches;
next	1.2;

1.2
date	2003.12.01.14.25.21;	author gorand;	state Exp;
branches;
next	1.1;

1.1
date	2003.11.30.12.30.04;	author gorand;	state Exp;
branches;
next	;


desc
@@


1.4
log
@added ECLK and NEC registers, all tests passed.
@
text
@TOOL:	ncelab	04.10-b001: Started on Dec 17, 2003 at 12:34:14
ncelab
    -f ncelab.args
        -MESSAGES
        -NOCOPYRIGHT
        -CDSLIB ../bin/cds.lib
        -HDLVAR ../bin/hdl.var
        -LOGFILE ../log/ncelab.log
        -SNAPSHOT worklib.bench:rtl
        -NO_TCHK_MSG
        -ACCESS +RWC
        worklib.tb_tasks
        worklib.gpio_testbench

	Elaborating the design hierarchy:
		Caching library 'worklib' ....... Done
	Building instance overlay tables: .................... Done
	Generating native compiled code:
		worklib.clkrst:v <0x67faf15a>
			streams:   2, words:  1034
		worklib.gpio_mon:v <0x50b5485b>
			streams:   6, words:  1408
		worklib.gpio_testbench:v <0x26ac113d>
			streams:   2, words:   300
		worklib.gpio_top:v <0x566f67ec>
			streams: 205, words: 164573
		worklib.tb_tasks:v <0x0ae72b6b>
			streams:  39, words: 57166
		worklib.wb_master:v <0x008f4b18>
			streams:  38, words: 21666
	Loading native compiled code:     .................... Done
	Building instance specific data structures.
	Design hierarchy summary:
		                  Instances  Unique
		Modules:                  6       6
		Registers:              130     130
		Scalar wires:            85       -
		Vectored wires:          13       -
		Always blocks:           56      56
		Initial blocks:           3       3
		Cont. assignments:       40      79
		Pseudo assignments:       2      49
		Simulation timescale:  10ps
	Writing initial simulation snapshot: worklib.bench:rtl
TOOL:	ncelab	04.10-b001: Exiting on Dec 17, 2003 at 12:34:15  (total: 00:00:01)
@


1.3
log
@changed by simulation.
@
text
@d1 1
a1 1
TOOL:	ncelab	04.10-b001: Started on Dec 09, 2003 at 12:18:09
d23 1
a23 1
		worklib.gpio_testbench:v <0x2b2f512c>
d25 6
a30 6
		worklib.gpio_top:v <0x2a4cd65a>
			streams:  72, words: 55544
		worklib.tb_tasks:v <0x3e6d21f9>
			streams:  33, words: 52966
		worklib.wb_master:v <0x2119db6d>
			streams:  38, words: 21648
d36 4
a39 4
		Registers:              122     122
		Scalar wires:            23       -
		Vectored wires:          14       -
		Always blocks:           24      24
d41 2
a42 2
		Cont. assignments:       10      17
		Pseudo assignments:       2      43
d45 1
a45 1
TOOL:	ncelab	04.10-b001: Exiting on Dec 09, 2003 at 12:18:10  (total: 00:00:01)
@


1.2
log
@changes, for VATS... script renamed, running with no arguments...
@
text
@d1 1
a1 1
TOOL:	ncelab	04.10-b001: Started on Dec 01, 2003 at 15:32:24
d45 1
a45 1
TOOL:	ncelab	04.10-b001: Exiting on Dec 01, 2003 at 15:32:26  (total: 00:00:02)
@


1.1
log
@added some files, needed for VATS...
@
text
@d1 1
a1 1
TOOL:	ncelab	04.10-b001: Started on Nov 30, 2003 at 13:20:32
d45 1
a45 1
TOOL:	ncelab	04.10-b001: Exiting on Nov 30, 2003 at 13:20:33  (total: 00:00:01)
@