head	1.2;
access;
symbols;
locks; strict;
comment	@# @;


1.2
date	2006.05.31.05.16.05;	author fisher5090;	state dead;
branches;
next	1.1;
commitid	1365447d26934567;

1.1
date	2006.01.26.13.08.14;	author fisher5090;	state Exp;
branches;
next	;
commitid	490a43d8c9904567;


desc
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1.2
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@# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = F:\10G\ethmac10g
SET speedgrade = -6
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
# SET outputdirectory = F:\10G\ethmac10g
SET device = xc2vp20
# SET projectname = F:\10G\ethmac10g
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = fg676
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex2p
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Synchronous_FIFO family Xilinx,_Inc. 5.0
# END Select
# BEGIN Parameters
CSET memory_type=Block_Memory
CSET write_acknowledge_flag=false
CSET data_width=64
CSET write_error_flag=false
CSET read_acknowledge_sense=Active_Low
CSET data_count_width=8
CSET fifo_depth=128
CSET component_name=rxdatafifo
CSET data_count=false
CSET read_acknowledge_flag=false
CSET read_error_sense=Active_Low
CSET read_error_flag=false
CSET write_acknowledge_sense=Active_Low
CSET write_error_sense=Active_Low
# END Parameters
GENERATE


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1.1
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@xilinx coregen
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