head 1.2; access; symbols; locks; strict; comment @# @; 1.2 date 2006.10.05.16.17.10; author petebleackley; state Exp; branches; next 1.1; commitid e2245252fbe4567; 1.1 date 2006.09.06.18.41.01; author petebleackley; state Exp; branches; next ; commitid 15ee44ff163a4567; desc @@ 1.2 log @Restored after CVS server crashed. Changed bitwidths and exp-golomb format to current specification. Placed copy of specification in docs directory @ text @Release 7.1.04i - xst H.42 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to __projnav CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s --> Reading design: divider.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) HDL Analysis 4) HDL Synthesis 5) Advanced HDL Synthesis 5.1) HDL Synthesis Report 6) Low Level Synthesis 7) Final Report 7.1) Device utilization summary 7.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "divider.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "divider" Output Format : NGC Target Device : xc2v2000-6-bg575 ---- Source Options Top Module Name : divider Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes ROM Style : Auto Mux Extraction : YES Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Equivalent register Removal : YES Slice Packing : YES Pack IO Registers into IOBs : auto ---- General Options Optimization Goal : Speed Optimization Effort : 2 Keep Hierarchy : NO Global Optimization : AllClockNets RTL Output : Yes Write Timing Constraints : NO Hierarchy Separator : _ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : divider.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO tristate2logic : Yes use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes enable_auto_floorplanning : No ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work. Architecture rtl of Entity divider is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 254x16-bit ROM for signal <$n0002> created at line 308. Found 16x8-bit multiplier for signal <$n0003> created at line 315. Found 8-bit subtractor for signal . Found 8-bit register for signal . Found 24-bit register for signal . Found 16-bit register for signal . Summary: inferred 1 ROM(s). inferred 40 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 1 Multiplier(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... INFO:Xst:1647 - Data output of ROM in block is tied to register in block . INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM. Advanced multiplier inference ... Found registered multiplier on signal <_n0003>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Block RAMs : 1 254x16-bit single-port block RAM : 1 # Multipliers : 1 16x8-bit registered multiplier : 1 # Adders/Subtractors : 1 8-bit subtractor : 1 # Registers : 1 8-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : divider.ngr Top Level Output File Name : divider Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 26 Macro Statistics : # RAM : 1 # 254x16-bit single-port block RAM: 1 # Registers : 8 # 1-bit register : 8 # Adders/Subtractors : 1 # 8-bit subtractor : 1 # Multipliers : 1 # 16x8-bit registered multiplier: 1 Cell Usage : # BELS : 13 # GND : 1 # LUT2 : 4 # LUT3 : 2 # LUT4 : 5 # VCC : 1 # FlipFlops/Latches : 8 # FDR : 7 # FDS : 1 # RAMS : 1 # RAMB16_S36 : 1 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 25 # IBUF : 17 # OBUF : 8 # MULTs : 1 # MULT18X18S : 1 ========================================================================= Device utilization summary: --------------------------- Selected Device : 2v2000bg575-6 Number of Slices: 6 out of 10752 0% Number of Slice Flip Flops: 8 out of 21504 0% Number of 4 input LUTs: 11 out of 21504 0% Number of bonded IOBs: 26 out of 408 6% Number of BRAMs: 1 out of 56 1% Number of MULT18X18s: 1 out of 56 1% Number of GCLKs: 1 out of 16 6% ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLOCK | BUFGP | 9 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -6 Minimum period: 3.832ns (Maximum Frequency: 260.994MHz) Minimum input arrival time before clock: 1.615ns Maximum output required time after clock: 5.229ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'CLOCK' Clock period: 3.832ns (frequency: 260.994MHz) Total number of paths / destination ports: 8 / 8 ------------------------------------------------------------------------- Delay: 3.832ns (Levels of Logic = 0) Source: NUMERATOR2_7 (FF) Destination: Mmult__n00031_inst_mult_0 (MULT) Source Clock: CLOCK rising Destination Clock: CLOCK rising Data Path: NUMERATOR2_7 to Mmult__n00031_inst_mult_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDR:C->Q 1 0.449 0.382 NUMERATOR2_7 (NUMERATOR2_7) MULT18X18S:B7 3.000 Mmult__n00031_inst_mult_0 ---------------------------------------- Total 3.832ns (3.449ns logic, 0.382ns route) (90.0% logic, 10.0% route) ========================================================================= Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK' Total number of paths / destination ports: 16 / 16 ------------------------------------------------------------------------- Offset: 1.615ns (Levels of Logic = 1) Source: RESET (PAD) Destination: NUMERATOR2_5 (FF) Destination Clock: CLOCK rising Data Path: RESET to NUMERATOR2_5 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 16 0.653 0.740 RESET_IBUF (RESET_IBUF) FDR:R 0.222 NUMERATOR2_2 ---------------------------------------- Total 1.615ns (0.875ns logic, 0.740ns route) (54.2% logic, 45.8% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK' Total number of paths / destination ports: 8 / 8 ------------------------------------------------------------------------- Offset: 5.229ns (Levels of Logic = 1) Source: Mmult__n00031_inst_mult_0 (MULT) Destination: QUOTIENT<7> (PAD) Source Clock: CLOCK rising Data Path: Mmult__n00031_inst_mult_0 to QUOTIENT<7> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ MULT18X18S:C->P15 1 1.103 0.383 Mmult__n00031_inst_mult_0 (QUOTIENT_7_OBUF) OBUF:I->O 3.743 QUOTIENT_7_OBUF (QUOTIENT<7>) ---------------------------------------- Total 5.229ns (4.846ns logic, 0.383ns route) (92.7% logic, 7.3% route) ========================================================================= CPU : 4.83 / 5.22 s | Elapsed : 5.00 / 5.00 s --> Total memory usage is 121148 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 3 ( 0 filtered) Number of infos : 2 ( 0 filtered) @ 1.1 log @Adaptive probability models now implemented in the decoder. Testbench for decoding added. Synthesis reports added to documentation section @ text @d4 1 a4 1 CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s d7 1 a7 1 CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s d35 1 a35 1 Target Device : xc2v250-6-cs144 d68 1 a68 1 Optimization Effort : 1 d98 1 a98 1 Compiling vhdl file "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" in Library work. d105 1 a105 1 WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch. d114 9 a122 12 Related source file is "C:/Xilinx/bin/ArithmeticDecoder/../ArithmeticCoder/Divider.vhd". WARNING:Xst:646 - Signal > is assigned but never used. WARNING:Xst:646 - Signal > is assigned but never used. Found 1022x32-bit ROM for signal <$n0002> created at line 1079. Found 16x10-bit multiplier for signal <$n0003> created at line 1086. Found 16x10-bit multiplier for signal <$n0004> created at line 1093. Found 10-bit subtractor for signal . Found 10-bit register for signal . Found 26-bit register for signal . Found 26-bit register for signal . Found 32-bit register for signal . Found 42-bit adder for signal . d125 3 a127 3 inferred 84 D-type flip-flop(s). inferred 2 Adder/Subtractor(s). inferred 2 Multiplier(s). a141 3 Found registered multiplier on signal <_n0004>: - 1 register level(s) found in a register connected to the multiplier macro ouput. Pushing register(s) into the multiplier macro. d150 5 a154 6 1022x32-bit single-port block RAM : 1 # Multipliers : 2 16x10-bit registered multiplier : 2 # Adders/Subtractors : 2 10-bit subtractor : 1 42-bit adder : 1 d156 1 a156 1 10-bit register : 1 d165 1 a165 1 Loading device for application Rf_Device from file '2v250.nph' in environment C:/Xilinx. d169 1 a169 1 Found area constraint ratio of 100 (+ 5) on block divider, actual ratio is 1. d182 1 a182 1 # IOs : 32 d186 7 a192 8 # 1022x32-bit single-port block RAM: 1 # Registers : 10 # 1-bit register : 10 # Adders/Subtractors : 2 # 10-bit subtractor : 1 # 42-bit adder : 1 # Multipliers : 2 # 16x10-bit registered multiplier: 2 d195 1 a195 1 # BELS : 69 d197 3 a199 3 # LUT1 : 5 # LUT2 : 20 # MUXCY : 23 d201 2 a202 3 # XORCY : 19 # FlipFlops/Latches : 10 # FDR : 9 d204 2 a205 2 # RAMS : 2 # RAMB16_S18 : 2 d208 5 a212 5 # IO Buffers : 31 # IBUF : 21 # OBUF : 10 # MULTs : 2 # MULT18X18S : 2 d218 1 a218 1 Selected Device : 2v250cs144-6 d220 6 a225 6 Number of Slices: 19 out of 1536 1% Number of Slice Flip Flops: 10 out of 3072 0% Number of 4 input LUTs: 25 out of 3072 0% Number of bonded IOBs: 32 out of 92 34% Number of BRAMs: 2 out of 24 8% Number of MULT18X18s: 2 out of 24 8% d241 1 a241 1 CLOCK | BUFGP | 12 | d248 3 a250 3 Minimum period: 3.967ns (Maximum Frequency: 252.048MHz) Minimum input arrival time before clock: 1.644ns Maximum output required time after clock: 8.362ns d259 2 a260 2 Clock period: 3.967ns (frequency: 252.048MHz) Total number of paths / destination ports: 20 / 20 d262 3 a264 3 Delay: 3.967ns (Levels of Logic = 0) Source: NUMERATOR2_9 (FF) Destination: Mmult__n00041_inst_mult_0 (MULT) d268 1 a268 1 Data Path: NUMERATOR2_9 to Mmult__n00041_inst_mult_0 d272 2 a273 2 FDR:C->Q 2 0.449 0.519 NUMERATOR2_9 (NUMERATOR2_9) MULT18X18S:B9 3.000 Mmult__n00041_inst_mult_0 d275 2 a276 2 Total 3.967ns (3.449ns logic, 0.519ns route) (86.9% logic, 13.1% route) d280 1 a280 1 Total number of paths / destination ports: 20 / 20 d282 1 a282 1 Offset: 1.644ns (Levels of Logic = 1) d284 1 a284 1 Destination: NUMERATOR2_7 (FF) d287 1 a287 1 Data Path: RESET to NUMERATOR2_7 d291 1 a291 1 IBUF:I->O 20 0.653 0.769 RESET_IBUF (RESET_IBUF) d294 2 a295 2 Total 1.644ns (0.875ns logic, 0.769ns route) (53.2% logic, 46.8% route) d299 1 a299 1 Total number of paths / destination ports: 299 / 10 d301 3 a303 3 Offset: 8.362ns (Levels of Logic = 9) Source: Mmult__n00041_inst_mult_0 (MULT) Destination: QUOTIENT<9> (PAD) d306 1 a306 1 Data Path: Mmult__n00041_inst_mult_0 to QUOTIENT<9> d310 2 a311 10 MULT18X18S:C->P25 1 2.073 0.548 Mmult__n00041_inst_mult_0 (PRODUCT2<25>) LUT2:I1->O 1 0.347 0.000 divider_QUOTIENT<3>lut (N23) MUXCY:S->O 1 0.235 0.000 divider_QUOTIENT<3>cy (divider_QUOTIENT<3>_cyo) MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<4>cy (divider_QUOTIENT<4>_cyo) MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<5>cy (divider_QUOTIENT<5>_cyo) MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<6>cy (divider_QUOTIENT<6>_cyo) MUXCY:CI->O 1 0.042 0.000 divider_QUOTIENT<7>cy (divider_QUOTIENT<7>_cyo) MUXCY:CI->O 0 0.042 0.000 divider_QUOTIENT<8>cy (divider_QUOTIENT<8>_cyo) XORCY:CI->O 1 0.824 0.383 divider_QUOTIENT<9>_xor (QUOTIENT_9_OBUF) OBUF:I->O 3.743 QUOTIENT_9_OBUF (QUOTIENT<9>) d313 2 a314 2 Total 8.362ns (7.432ns logic, 0.930ns route) (88.9% logic, 11.1% route) d317 1 a317 1 CPU : 5.28 / 5.66 s | Elapsed : 5.00 / 5.00 s d321 1 a321 1 Total memory usage is 101628 kilobytes @