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1.1
date     2008.01.16.19.01.34;  author fellnhofer;  state Exp;
branches 1.1.1.1;
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commitid        122547a751ef4567;

1.1.1.1
date     2008.01.16.19.01.34;  author fellnhofer;  state Exp;
branches ;
next     ;
commitid        122547a751ef4567;


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@Release 9.2i Map J.36
Xilinx Map Application Log File for Design 'sio'

Design Information
------------------
Command Line   : map -ise /home/andi/xilinx/rs232/rs232.ise -intstyle ise -p
xc3s500e-fg320-5 -cm area -pr b -k 4 -c 100 -o sio_map.ncd sio.ngd sio.pcf 
Target Device  : xc3s500e
Target Package : fg320
Target Speed   : -5
Mapper Version : spartan3e -- $Revision: 1.36 $
Mapped Date    : Tue Nov 13 12:05:41 2007

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Number of Slice Flip Flops:         153 out of   9,312    1%
  Number of 4 input LUTs:             171 out of   9,312    1%
Logic Distribution:
  Number of occupied Slices:                          140 out of   4,656    3%
    Number of Slices containing only related logic:     140 out of     140  100%
    Number of Slices containing unrelated logic:          0 out of     140    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:            212 out of   9,312    2%
  Number used as logic:                171
  Number used as a route-thru:          40
  Number used as Shift registers:        1
  Number of bonded IOBs:               12 out of     232    5%
    IOB Flip Flops:                     9
  Number of Block RAMs:                1 out of      20    5%
  Number of GCLKs:                     1 out of      24    4%

Total equivalent gate count for design:  68,222
Additional JTAG gate count for IOBs:  576
Peak Memory Usage:  145 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   3 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "sio_map.mrp" for details.
@


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