head     1.1;
branch   1.1.1;
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symbols  initial:1.1.1.1 diogenes:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2008.01.16.19.01.36;  author fellnhofer;  state Exp;
branches 1.1.1.1;
next     ;
commitid        122547a751ef4567;

1.1.1.1
date     2008.01.16.19.01.36;  author fellnhofer;  state Exp;
branches ;
next     ;
commitid        122547a751ef4567;


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1.1
log
@Initial revision
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@Welcome to Xilinx CORE Generator.
Opened project file /home/andi/xilinx/rs232/cpu/coregen.cgp.
Created directory /home/andi/xilinx/rs232/vga/coregen.
Closed project file.
Wrote project file /home/andi/xilinx/rs232/vga/coregen/coregen.cgp.
Customizing IP...
Finished Customizing.
Generating IP...
ERROR:coreutil - Failure to set parameters on core: Some initial values do not
   match either the Memory Initialization Radix or Data Width. Press the Show
   Values button to view them.
ERROR:coreutil - Failure to generate output products
ERROR:coreutil - An error occurred while running Java. Please examine the
   console or coregen log file for a specific IP related error.
   If there is no specific error the problem may be due to memory limitations.
   For more information please consult solution record 21955 available from:
   http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21955Finished Generating.
ERROR:sim:57 - Error found during generation
Customizing IP...
Cancelled Customization.
Customizing IP...
ERROR:coreutil - Must enter a component name.
Finished Customizing.
Generating IP...
Generating Implementation files.
Generating the VHDL wrapper.
Generating the VHDL instantiation template.
Generating NGC file.
Finished Generating.
Successfully generated video_ram.
Closed project file.
@


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