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1.1
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1.1.1.1
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desc
@@


1.1
log
@Initial revision
@
text
@V3 12
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/10/31.09:40:20 I.33
PH work/vga_pckg 1162399259        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491 \
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1162399258 CD vga
EN work/vga 1162399260             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491 \
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1162399258
AR work/vga/vga_arch 1162399261    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1162399260 \
      CP sync
EN work/sync 1162399262            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491 \
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1162399258
AR work/sync/sync_arch 1162399263  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1162399262
FL $XILINX/ISEexamples/cpu8080/common.vhd 2006/10/16.23:07:12 I.33
PH work/common 1162399257          FL $XILINX/ISEexamples/cpu8080/common.vhd \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491
PB work/common 1162399258          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1162399257 \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491
@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@d1 3
a3 3
V3 17
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/11/09.08:44:32 I.33
PH work/vga_pckg 1163234707        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163234703 CD vga
EN work/vga 1163234708             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163234703
AR work/vga/vga_arch 1163234709    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163234708 \
d11 1
a11 1
EN work/sync 1163234710            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 2
a14 9
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163234703
AR work/sync/sync_arch 1163234711  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163234710
FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd 2006/11/08.21:59:14 I.33
PH work/ps2_kbd_pckg 1163234704    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491 CD ps2_kbd
EN work/ps2_kbd 1163234705         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      PB ieee/std_logic_1164 1152316480 PH ieee/NUMERIC_STD 1152316491
AR work/ps2_kbd/arch 1163234706    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163234705
d16 1
a16 1
PH work/common 1163234702          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d18 1
a18 1
PB work/common 1163234703          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163234702 \
@


1.1.1.3
log
@8080 CPU project
@
text
@d2 2
a3 2
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/11/15.08:45:56 I.33
PH work/vga_pckg 1163609205        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163609201 CD vga
EN work/vga 1163609206             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163609201
AR work/vga/vga_arch 1163609207    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163609206 \
d11 1
a11 1
EN work/sync 1163609208            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 2
a14 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163609201
AR work/sync/sync_arch 1163609209  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163609208
d16 1
a16 1
PH work/ps2_kbd_pckg 1163609202    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d18 1
a18 1
EN work/ps2_kbd 1163609203         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d20 2
a21 2
AR work/ps2_kbd/arch 1163609204    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163609203
d23 1
a23 1
PH work/common 1163609200          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d25 1
a25 1
PB work/common 1163609201          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163609200 \
@


1.1.1.4
log
@8080 CPU project
@
text
@d3 1
a3 1
PH work/vga_pckg 1163739273        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163739269 CD vga
EN work/vga 1163739274             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163739269
AR work/vga/vga_arch 1163739275    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163739274 \
d11 1
a11 1
EN work/sync 1163739276            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 2
a14 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163739269
AR work/sync/sync_arch 1163739277  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163739276
d16 1
a16 1
PH work/ps2_kbd_pckg 1163739270    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d18 1
a18 1
EN work/ps2_kbd 1163739271         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d20 2
a21 2
AR work/ps2_kbd/arch 1163739272    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163739271
d23 1
a23 1
PH work/common 1163739268          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d25 1
a25 1
PB work/common 1163739269          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163739268 \
@


1.1.1.5
log
@8080 CPU project
@
text
@d3 1
a3 1
PH work/vga_pckg 1163898461        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163898457 CD vga
EN work/vga 1163898462             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163898457
AR work/vga/vga_arch 1163898463    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163898462 \
d11 1
a11 1
EN work/sync 1163898464            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 2
a14 2
      PH unisim/VCOMPONENTS 1154399716 PB work/common 1163898457
AR work/sync/sync_arch 1163898465  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163898464
d16 1
a16 1
PH work/ps2_kbd_pckg 1163898458    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d18 1
a18 1
EN work/ps2_kbd 1163898459         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d20 2
a21 2
AR work/ps2_kbd/arch 1163898460    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163898459
d23 1
a23 1
PH work/common 1163898456          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d25 1
a25 1
PB work/common 1163898457          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163898456 \
@