head 1.1; branch 1.1.1; access; symbols add:1.1.1.3 update:1.1.1.5 initial:1.1.1.1 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.10.06.20.06.25; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 55f24526b7374567; 1.1.1.1 date 2006.10.06.20.06.25; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 55f24526b7374567; 1.1.1.2 date 2006.10.21.08.40.09; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 72bf4539dcde4567; 1.1.1.3 date 2006.11.01.19.52.30; author samiam95124; state Exp; branches; next 1.1.1.4; commitid 31604548faf04567; 1.1.1.4 date 2006.11.17.10.44.20; author samiam95124; state Exp; branches; next 1.1.1.5; commitid 3e01455d92754567; 1.1.1.5 date 2006.11.19.04.16.10; author samiam95124; state Exp; branches; next ; commitid 3554455fda5a4567; desc @@ 1.1 log @Initial revision @ text @set -tmpdir "./xst/projnav.tmp" elaborate -ifn testbench.prj -ifmt mixed @ 1.1.1.1 log @8080 CPU project @ text @@ 1.1.1.2 log @8080 CPU project @ text @d2 1 a2 2 set -xsthdpdir "./xst" run a4 48 -ofn testbench -ofmt NGC -p xc3s200-5-pq208 -top testbench -opt_mode Speed -opt_level 1 -iuc NO -lso testbench.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 @ 1.1.1.3 log @8080 CPU project @ text @d8 1 a8 1 -p xc3s1000-4-ft256 @ 1.1.1.4 log @8080 CPU project @ text @d2 2 a3 1 elaborate d6 48 @ 1.1.1.5 log @8080 CPU project @ text @d2 1 a2 2 set -xsthdpdir "./xst" run a4 48 -ofn testbench -ofmt NGC -p xc3s1000-4-ft256 -top testbench -opt_mode Speed -opt_level 1 -iuc NO -lso testbench.lso -keep_hierarchy NO -rtlview Yes -glob_opt AllClockNets -read_cores YES -write_timing_constraints NO -cross_clock_analysis NO -hierarchy_separator / -bus_delimiter <> -case maintain -slice_utilization_ratio 100 -verilog2001 YES -fsm_extract YES -fsm_encoding Auto -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -rom_style Auto -mux_extract YES -resource_sharing YES -mult_style auto -iobuf YES -max_fanout 500 -bufg 8 -register_duplication YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Yes -use_sync_set Yes -use_sync_reset Yes -iob auto -equivalent_register_removal YES -slice_utilization_ratio_maxmargin 5 @