head 1.1; branch 1.1.1; access; symbols add:1.1.1.1 update:1.1.1.5 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.11.01.19.56.19; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 31604548faf04567; 1.1.1.1 date 2006.11.01.19.56.19; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 31604548faf04567; 1.1.1.2 date 2006.11.11.11.58.45; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 1fa44555b9f14567; 1.1.1.3 date 2006.11.16.10.22.46; author samiam95124; state Exp; branches; next 1.1.1.4; commitid 3f6c455c3ae54567; 1.1.1.4 date 2006.11.17.10.48.28; author samiam95124; state Exp; branches; next 1.1.1.5; commitid 3e01455d92754567; 1.1.1.5 date 2006.11.19.04.23.42; author samiam95124; state Exp; branches; next ; commitid 3554455fda5a4567; desc @@ 1.1 log @Initial revision @ text @Release 8.2.02i par I.33 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. SCOTT-H-PC:: Wed Nov 01 08:45:45 2006 par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf Constraints file: testbench.pcf. Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx. "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". Device speed data version: "PRODUCTION 1.39 2006-07-07". Device Utilization Summary: Number of BUFGMUXs 3 out of 8 37% Number of External IOBs 44 out of 173 25% Number of LOCed IOBs 44 out of 44 100% Number of MULT18X18s 1 out of 24 4% Number of RAMB16s 2 out of 24 8% Number of Slices 3425 out of 7680 44% Number of SLICEMs 950 out of 3840 24% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting Placer Phase 1.1 Phase 1.1 (Checksum:996b76) REAL time: 9 secs Phase 2.7 Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs Phase 3.31 Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs Phase 4.2 ...... .................. Phase 4.2 (Checksum:98bdbb) REAL time: 22 secs Phase 5.8 ...................................................................................................................................................................................................................................... .............. ....................................................................................................................... ................. .................... ......................................................... Phase 5.8 (Checksum:ad58a9) REAL time: 3 mins 6 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 3 mins 6 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 4 mins 29 secs Phase 8.5 Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 mins 29 secs Writing design to file testbench.ncd Total REAL time to Placer completion: 4 mins 34 secs Total CPU time to Placer completion: 3 mins 57 secs Starting Router Phase 1: 26573 unrouted; REAL time: 4 mins 34 secs Phase 2: 24811 unrouted; REAL time: 4 mins 40 secs Phase 3: 7304 unrouted; REAL time: 4 mins 47 secs Phase 4: 7304 unrouted; (26511) REAL time: 4 mins 48 secs Phase 5: 7292 unrouted; (0) REAL time: 4 mins 53 secs Phase 6: 0 unrouted; (0) REAL time: 5 mins 11 secs Phase 7: 0 unrouted; (0) REAL time: 5 mins 15 secs WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because 332 NON-CLK pins failed to route using a CLK template. WARNING:Route:447 - CLK Net:clkdiv<3> may have excessive skew because 1 NON-CLK pins failed to route using a CLK template. Total REAL time to Router completion: 5 mins 15 secs Total CPU time to Router completion: 4 mins 34 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | reset_n_BUFGP | BUFGMUX5| No | 348 | 0.159 | 1.033 | +---------------------+--------------+------+------+------------+-------------+ | clkdiv<3> | BUFGMUX2| No | 287 | 0.436 | 1.140 | +---------------------+--------------+------+------+------------+-------------+ | clock_BUFGP | BUFGMUX0| No | 1266 | 0.519 | 1.221 | +---------------------+--------------+------+------+------------+-------------+ |select1/selectd/_and | | | | | | | 0000 | Local| | 7 | 0.011 | 2.195 | +---------------------+--------------+------+------+------------+-------------+ |select1/selecta/_and | | | | | | | 0000 | Local| | 7 | 0.143 | 3.148 | +---------------------+--------------+------+------+------------+-------------+ |select1/selectb/_and | | | | | | | 0000 | Local| | 7 | 0.066 | 2.239 | +---------------------+--------------+------+------+------------+-------------+ |select1/selectc/_and | | | | | | | 0000 | Local| | 7 | 0.120 | 2.850 | +---------------------+--------------+------+------+------------+-------------+ * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0 The AVERAGE CONNECTION DELAY for this design is: 2.120 The MAXIMUM PIN DELAY IS: 12.443 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 9.291 Listing Pin Delays by value: (nsec) d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 13.00 d >= 13.00 --------- --------- --------- --------- --------- --------- 15385 8001 2840 587 73 0 Timing Score: 0 Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Requested | Actual | Logic | Absolute |Number of | | | Levels | Slack |errors ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net clk | N/A | 23.680ns | 3 | N/A | N/A div<3> | | | | | ------------------------------------------------------------------------------------------------------ Autotimespec constraint for clock net clo | N/A | 33.066ns | 12 | N/A | N/A ck_BUFGP | | | | | ------------------------------------------------------------------------------------------------------ All constraints were met. INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 mins 25 secs Total CPU time to PAR completion: 4 mins 42 secs Peak Memory Usage: 263 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Number of error messages: 0 Number of warning messages: 2 Number of info messages: 1 Writing design to file testbench.ncd PAR done! @ 1.1.1.1 log @8080 CPU project @ text @@ 1.1.1.2 log @8080 CPU project @ text @d4 1 a4 1 SCOTT-H-PC:: Sat Nov 11 00:49:50 2006 d27 3 a29 3 Number of BUFGMUXs 2 out of 8 25% Number of External IOBs 54 out of 173 31% Number of LOCed IOBs 46 out of 54 85% d32 3 a34 3 Number of RAMB16s 3 out of 24 12% Number of Slices 3312 out of 7680 43% Number of SLICEMs 964 out of 3840 25% d47 1 a47 1 Phase 1.1 (Checksum:996f21) REAL time: 11 secs d50 1 a50 14 WARNING:Place:837 - Partially locked IO Bus is found. Following components of the bus are not locked: Comp: addr<15> Comp: addr<14> Comp: addr<13> Comp: addr<12> Comp: addr<11> Comp: addr<10> Comp: addr<9> Comp: addr<8> INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more). Phase 2.7 (Checksum:1312cfe) REAL time: 11 secs d53 1 a53 1 Phase 3.31 (Checksum:1c9c37d) REAL time: 11 secs d56 2 a57 2 ..... ................... d60 1 a60 1 Phase 4.2 (Checksum:98bdc7) REAL time: 22 secs d62 8 a69 2 Phase 5.3 Phase 5.3 (Checksum:2faf07b) REAL time: 22 secs d72 1 a72 1 Phase 6.5 (Checksum:39386fa) REAL time: 23 secs d74 2 a75 8 Phase 7.8 ....................................................................................................................................................................................................................................... ......... ............................................................................................. .................. ............ ..................................................................................................................................................................................................... Phase 7.8 (Checksum:13e75c6) REAL time: 2 mins 56 secs d78 1 a78 7 Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins 57 secs Phase 9.18 Phase 9.18 (Checksum:55d4a77) REAL time: 4 mins 9 secs Phase 10.5 Phase 10.5 (Checksum:5f5e0f6) REAL time: 4 mins 9 secs d83 2 a84 2 Total REAL time to Placer completion: 4 mins 14 secs Total CPU time to Placer completion: 3 mins 33 secs d88 1 a88 1 Phase 1: 26804 unrouted; REAL time: 4 mins 14 secs d90 1 a90 1 Phase 2: 25251 unrouted; REAL time: 4 mins 27 secs d92 1 a92 1 Phase 3: 7585 unrouted; REAL time: 4 mins 37 secs d94 1 a94 1 Phase 4: 7585 unrouted; (20316) REAL time: 4 mins 37 secs d96 1 a96 1 Phase 5: 7586 unrouted; (0) REAL time: 4 mins 40 secs d103 3 a105 1 442 NON-CLK pins failed to route using a CLK template. d107 2 a108 2 Total REAL time to Router completion: 5 mins 16 secs Total CPU time to Router completion: 4 mins 25 secs d126 3 a128 1 | clock_BUFGP | BUFGMUX3| No | 1338 | 0.485 | 1.185 | d130 1 a130 1 | reset_n_BUFGP | BUFGMUX5| No | 458 | 0.200 | 0.960 | d132 2 a133 2 |select1/selectb/_and | | | | | | | 0000 | Local| | 7 | 0.166 | 2.998 | d136 4 a139 1 | 0000 | Local| | 7 | 0.278 | 2.413 | d142 1 a142 4 | 0000 | Local| | 7 | 0.025 | 2.148 | +---------------------+--------------+------+------+------------+-------------+ |select1/selectd/_and | | | | | | | 0000 | Local| | 7 | 0.135 | 2.994 | d156 3 a158 3 The AVERAGE CONNECTION DELAY for this design is: 2.358 The MAXIMUM PIN DELAY IS: 10.245 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.763 d162 1 a162 1 d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 11.00 d >= 11.00 d164 1 a164 1 14013 8132 4035 824 140 0 d175 4 a178 1 Autotimespec constraint for clock net clo | N/A | 22.020ns | 10 | N/A | N/A d192 2 a193 2 Total REAL time to PAR completion: 5 mins 26 secs Total CPU time to PAR completion: 4 mins 32 secs d195 1 a195 1 Peak Memory Usage: 265 MB d202 1 a202 1 Number of info messages: 2 @ 1.1.1.3 log @8080 CPU project @ text @d4 1 a4 1 SCOTT-H-PC:: Wed Nov 15 08:50:34 2006 d31 4 a34 4 Number of MULT18X18s 2 out of 24 8% Number of RAMB16s 4 out of 24 16% Number of Slices 3458 out of 7680 45% Number of SLICEMs 958 out of 3840 24% d47 1 a47 1 Phase 1.1 (Checksum:9984aa) REAL time: 9 secs d63 1 a63 1 Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs d66 1 a66 1 Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs d73 1 a73 1 Phase 4.2 (Checksum:98bdc7) REAL time: 18 secs d76 1 a76 1 Phase 5.3 (Checksum:2faf07b) REAL time: 18 secs d79 1 a79 1 Phase 6.5 (Checksum:39386fa) REAL time: 19 secs d82 7 a88 7 ..................................................... ..................................... ............................................................................................................................................................................... ....... ....... ..... Phase 7.8 (Checksum:1191c59) REAL time: 2 mins 2 secs d91 1 a91 1 Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins 2 secs d94 1 a94 1 Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 53 secs d97 1 a97 1 Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 53 secs d102 2 a103 2 Total REAL time to Placer completion: 2 mins 57 secs Total CPU time to Placer completion: 2 mins 51 secs d107 1 a107 5 Phase 1: 27686 unrouted; REAL time: 2 mins 57 secs Phase 2: 26061 unrouted; REAL time: 3 mins 6 secs Phase 3: 8086 unrouted; REAL time: 3 mins 13 secs d109 1 a109 1 Phase 4: 8086 unrouted; (44628) REAL time: 3 mins 13 secs d111 1 a111 1 Phase 5: 8305 unrouted; (0) REAL time: 3 mins 17 secs d113 1 a113 1 Phase 6: 0 unrouted; (12079) REAL time: 3 mins 42 secs d115 1 a115 1 Phase 7: 0 unrouted; (12079) REAL time: 3 mins 45 secs d117 1 a117 1 Phase 8: 0 unrouted; (3768) REAL time: 4 mins d119 1 a119 1 Phase 9: 0 unrouted; (3768) REAL time: 4 mins 2 secs d122 1 a122 1 463 NON-CLK pins failed to route using a CLK template. d124 2 a125 2 Total REAL time to Router completion: 4 mins 2 secs Total CPU time to Router completion: 3 mins 57 secs d143 1 a143 1 | clock_BUFGP | BUFGMUX3| No | 1384 | 0.436 | 1.139 | d145 1 a145 1 | reset_n_BUFGP | BUFGMUX5| No | 479 | 0.196 | 0.916 | d147 2 a148 2 |select1/selectc/_and | | | | | | | 0000 | Local| | 7 | 0.008 | 2.121 | d151 4 a154 1 | 0000 | Local| | 7 | 0.038 | 2.244 | d157 1 a157 4 | 0000 | Local| | 7 | 0.083 | 2.850 | +---------------------+--------------+------+------+------------+-------------+ |select1/selectb/_and | | | | | | | 0000 | Local| | 7 | 0.061 | 2.289 | d171 3 a173 3 The AVERAGE CONNECTION DELAY for this design is: 2.329 The MAXIMUM PIN DELAY IS: 10.680 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 9.230 d179 1 a179 1 14637 7957 4563 746 81 0 d190 1 a190 1 Autotimespec constraint for clock net clo | N/A | 19.923ns | 9 | N/A | N/A d204 2 a205 2 Total REAL time to PAR completion: 4 mins 9 secs Total CPU time to PAR completion: 4 mins 2 secs d207 1 a207 1 Peak Memory Usage: 282 MB @ 1.1.1.4 log @8080 CPU project @ text @d4 1 a4 1 SCOTT-H-PC:: Thu Nov 16 20:11:54 2006 d33 1 a33 1 Number of Slices 3445 out of 7680 44% d47 1 a47 1 Phase 1.1 (Checksum:99838d) REAL time: 8 secs d53 7 a59 10 WARNING:Place:837 - Partially locked IO Bus is found. Following components of the bus are not locked: Comp: diag<6> Comp: diag<5> Comp: diag<4> Comp: diag<3> Comp: diag<2> Comp: diag<1> Comp: diag<0> d63 1 a63 1 Phase 2.7 (Checksum:1312cfe) REAL time: 8 secs d66 1 a66 1 Phase 3.31 (Checksum:1c9c37d) REAL time: 8 secs d73 1 a73 1 Phase 4.2 (Checksum:98bdc7) REAL time: 16 secs d76 1 a76 1 Phase 5.3 (Checksum:2faf07b) REAL time: 17 secs d79 1 a79 1 Phase 6.5 (Checksum:39386fa) REAL time: 17 secs d82 7 a88 7 ...................................................................................................................................................................................... ......... ....................................................................................................................................................... .......... ............ ....................... Phase 7.8 (Checksum:124efe7) REAL time: 1 mins 42 secs d91 1 a91 1 Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 mins 42 secs d94 1 a94 1 Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 44 secs d97 1 a97 1 Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 44 secs d102 2 a103 2 Total REAL time to Placer completion: 2 mins 48 secs Total CPU time to Placer completion: 2 mins 42 secs d107 1 a107 1 Phase 1: 27650 unrouted; REAL time: 2 mins 49 secs d109 1 a109 1 Phase 2: 26038 unrouted; REAL time: 2 mins 57 secs d111 1 a111 1 Phase 3: 8278 unrouted; REAL time: 3 mins 4 secs d113 1 a113 1 Phase 4: 8278 unrouted; (42106) REAL time: 3 mins 4 secs d115 1 a115 1 Phase 5: 8305 unrouted; (0) REAL time: 3 mins 7 secs d117 1 a117 1 Phase 6: 0 unrouted; (8000) REAL time: 3 mins 44 secs d119 1 a119 1 Phase 7: 0 unrouted; (8000) REAL time: 3 mins 47 secs d121 1 a121 1 Phase 8: 0 unrouted; (5730) REAL time: 4 mins d123 1 a123 1 Phase 9: 0 unrouted; (5730) REAL time: 4 mins 9 secs d126 1 a126 1 462 NON-CLK pins failed to route using a CLK template. d128 1 a128 1 Total REAL time to Router completion: 4 mins 9 secs d147 1 a147 1 | clock_BUFGP | BUFGMUX3| No | 1382 | 0.433 | 1.139 | d149 1 a149 1 | reset_n_BUFGP | BUFGMUX5| No | 478 | 0.155 | 1.085 | d152 1 a152 1 | 0000 | Local| | 7 | 0.156 | 3.257 | d155 1 a155 1 | 0000 | Local| | 7 | 0.085 | 2.938 | d158 1 a158 1 | 0000 | Local| | 7 | 0.131 | 2.884 | d161 1 a161 1 | 0000 | Local| | 7 | 0.079 | 2.261 | d175 3 a177 3 The AVERAGE CONNECTION DELAY for this design is: 2.351 The MAXIMUM PIN DELAY IS: 9.448 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.536 d181 1 a181 1 d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 10.00 d >= 10.00 d183 1 a183 1 14494 8705 3462 1202 93 0 d194 1 a194 1 Autotimespec constraint for clock net clo | N/A | 20.711ns | 4 | N/A | N/A d208 1 a208 1 Total REAL time to PAR completion: 4 mins 20 secs d211 1 a211 1 Peak Memory Usage: 283 MB d217 1 a217 1 Number of warning messages: 3 @ 1.1.1.5 log @8080 CPU project @ text @d4 1 a4 1 SCOTT-H-PC:: Sat Nov 18 17:12:12 2006 d33 1 a33 1 Number of Slices 3447 out of 7680 44% d47 1 a47 1 Phase 1.1 (Checksum:998412) REAL time: 11 secs d66 1 a66 1 Phase 2.7 (Checksum:1312cfe) REAL time: 11 secs d69 1 a69 1 Phase 3.31 (Checksum:1c9c37d) REAL time: 11 secs d76 1 a76 1 Phase 4.2 (Checksum:98bdc7) REAL time: 21 secs d79 1 a79 1 Phase 5.3 (Checksum:2faf07b) REAL time: 21 secs d82 1 a82 1 Phase 6.5 (Checksum:39386fa) REAL time: 22 secs d85 3 a87 1 ....................................................................................................................................................................................................... d89 3 a91 5 ................................................................................................................................................... ......... ......... .............. Phase 7.8 (Checksum:11c59cb) REAL time: 2 mins d94 1 a94 1 Phase 8.5 (Checksum:4c4b3f8) REAL time: 2 mins d97 1 a97 1 Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 47 secs d100 1 a100 1 Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 47 secs d105 2 a106 2 Total REAL time to Placer completion: 2 mins 51 secs Total CPU time to Placer completion: 2 mins 37 secs d110 5 a114 1 Phase 1: 27602 unrouted; REAL time: 2 mins 52 secs d116 1 a116 1 Phase 2: 25995 unrouted; REAL time: 3 mins 1 secs d118 1 a118 1 Phase 3: 8138 unrouted; REAL time: 3 mins 9 secs d120 1 a120 1 Phase 4: 8138 unrouted; (22222) REAL time: 3 mins 9 secs d122 1 a122 1 Phase 5: 8108 unrouted; (0) REAL time: 3 mins 12 secs d124 1 a124 1 Phase 6: 0 unrouted; (0) REAL time: 3 mins 44 secs d126 1 a126 1 Phase 7: 0 unrouted; (0) REAL time: 3 mins 48 secs d129 1 a129 1 464 NON-CLK pins failed to route using a CLK template. d131 2 a132 2 Total REAL time to Router completion: 3 mins 48 secs Total CPU time to Router completion: 3 mins 31 secs d150 1 a150 1 | clock_BUFGP | BUFGMUX3| No | 1378 | 0.461 | 1.164 | d152 1 a152 1 | reset_n_BUFGP | BUFGMUX5| No | 480 | 0.251 | 0.972 | d155 1 a155 1 | 0000 | Local| | 7 | 0.187 | 3.279 | d158 1 a158 1 | 0000 | Local| | 7 | 0.048 | 2.205 | d161 1 a161 1 | 0000 | Local| | 7 | 0.193 | 2.324 | d164 1 a164 1 | 0000 | Local| | 7 | 0.177 | 2.932 | d178 3 a180 3 The AVERAGE CONNECTION DELAY for this design is: 2.287 The MAXIMUM PIN DELAY IS: 9.510 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 8.894 d186 1 a186 1 14560 8731 3770 745 98 0 d197 1 a197 1 Autotimespec constraint for clock net clo | N/A | 20.098ns | 8 | N/A | N/A d211 2 a212 2 Total REAL time to PAR completion: 3 mins 56 secs Total CPU time to PAR completion: 3 mins 38 secs d214 1 a214 1 Peak Memory Usage: 269 MB @