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1.1
date	2006.11.01.20.02.07;	author samiam95124;	state Exp;
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	1.1.1.1;
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1.1.1.1
date	2006.11.01.20.02.07;	author samiam95124;	state Exp;
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1.1.1.2
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desc
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1.1
log
@Initial revision
@
text
@Release 8.2.02i reportgen I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

SCOTT-H-PC::  Sat Oct 28 20:52:32 2006

C:\Xilinx\bin\nt\reportgen.exe -intstyle ise -delay -o testbench_last_par
testbench_last_par.ncd 

Loading device for application Rf_Device from file '3s1000.nph' in environment
C:\Xilinx.
   "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
ReportGen:LoadDesign: 'testbench_last_par.ncd'
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version:  "PRODUCTION 1.39 2006-07-07".

Generating Delay Report: testbench_last_par.dly


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.453
   The MAXIMUM PIN DELAY IS:                              11.917
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:  10.027

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 12.00  d >= 12.00
   ---------   ---------   ---------   ---------   ---------   ---------
       12586        7604        4376         822         215           0


**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         clock_BUFGP |      BUFGMUX0| No   | 1244 |  0.453     |  1.153      |
+---------------------+--------------+------+------+------------+-------------+
|       reset_n_BUFGP |      BUFGMUX7| No   |  351 |  0.159     |  0.995      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selecta/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  1.950     |  2.312      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectb/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.215     |  3.461      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectc/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.227     |  3.201      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectd/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.128     |  3.107      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

reportgen done!
@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@d4 1
a4 1
SCOTT-H-PC::  Sat Nov 04 19:31:52 2006
d6 2
a7 1
C:\Xilinx\bin\nt\reportgen.exe -intstyle ise -delay -o testbench testbench.ncd 
d12 1
a12 1
ReportGen:LoadDesign: 'testbench.ncd'
d18 1
a18 1
Generating Delay Report: testbench.dly
d26 3
a28 3
   The AVERAGE CONNECTION DELAY for this design is:        2.105
   The MAXIMUM PIN DELAY IS:                              10.487
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   9.285
d32 1
a32 1
    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 11.00  d >= 11.00
d34 1
a34 1
       15626        8599        2634         525         124           0
d44 1
a44 1
|       reset_n_BUFGP |      BUFGMUX5| No   |  418 |  0.182     |  0.987      |
d46 1
a46 1
|         clock_BUFGP |      BUFGMUX0| No   | 1564 |  0.451     |  1.154      |
d49 1
a49 4
|                0000 |         Local|      |    7 |  0.067     |  2.166      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectd/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.931     |  1.779      |
d52 1
a52 1
|                0000 |         Local|      |    7 |  0.048     |  1.842      |
d55 4
a58 1
|                0000 |         Local|      |    7 |  0.007     |  2.251      |
@