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desc
@@


1.1
log
@Initial revision
@
text
@V3 20
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/10/06.10:03:50 I.33
MO work/cpu8080         FL $XILINX/ISEexamples/cpu8080/cpu8080.v MI alu
MO work/alu             FL $XILINX/ISEexamples/cpu8080/cpu8080.v
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/10/06.10:02:50 I.33
MO work/testbench       FL $XILINX/ISEexamples/cpu8080/testbench.v MI cpu8080 \
      MI ram            MI rom            MI select
MO work/select          FL $XILINX/ISEexamples/cpu8080/testbench.v MI selectone
MO work/selectone       FL $XILINX/ISEexamples/cpu8080/testbench.v
MO work/rom             FL $XILINX/ISEexamples/cpu8080/testbench.v
MO work/ram             FL $XILINX/ISEexamples/cpu8080/testbench.v
FL $XILINX/verilog/src/glbl.v 2006/05/17.11:09:08 I.33
MO work/glbl            FL $XILINX/verilog/src/glbl.v
FL $XILINX/ISEexamples/cpu8080/cpu_tbw.tfw 2006/09/23.19:23:18 I.33
MO work/cpu_tbw         FL $XILINX/ISEexamples/cpu8080/cpu_tbw.tfw MI testbench
@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@d1 2
a2 2
V3 23
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/10/20.22:31:24 I.33
d5 1
a5 2
FL test.lst 2006/10/20.22:03:36 I.33
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/10/20.22:07:46 I.33 FL test.lst
d7 1
a7 1
      MI intcontrol     MI ram            MI rom            MI select
a9 1
MO work/intcontrol      FL $XILINX/ISEexamples/cpu8080/testbench.v
d14 1
a14 1
FL $XILINX/ISEexamples/cpu8080/cpu_tbw.tfw 2006/10/20.21:19:58 I.33
@


1.1.1.3
log
@8080 CPU project
@
text
@d1 2
a2 17
V3 45
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/10/31.09:40:20 I.33
PH work/vga_pckg 1162362489        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794 \
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1162002891 CD vga
EN work/vga 1162362490             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794 \
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1162002891
AR work/vga/vga_arch 1162362491    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1162362490 \
      CP sync
EN work/sync 1162362492            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794 \
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1162002891
AR work/sync/sync_arch 1162362493  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1162362492
FL $XILINX/ISEexamples/cpu8080/cpu_tbw.ant 2006/10/28.09:13:00 I.33
MO work/cpu_tbw         FL $XILINX/ISEexamples/cpu8080/cpu_tbw.ant MI testbench
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/10/29.08:05:44 I.33
d5 2
a6 9
FL $XILINX/ISEexamples/cpu8080/vgachr.v 2006/10/31.23:18:10 I.33
MO work/terminal        FL $XILINX/ISEexamples/cpu8080/vgachr.v MI chrmemmap
MO work/chrmemmap       FL $XILINX/ISEexamples/cpu8080/vgachr.v MI chrrom MI vga
MO work/chrrom          FL $XILINX/ISEexamples/cpu8080/vgachr.v
FL $XILINX/ISEexamples/cpu8080/cpu8080_tbw.tfw 2006/10/28.22:18:08 I.33
MO work/cpu8080_tbw     FL $XILINX/ISEexamples/cpu8080/cpu8080_tbw.tfw \
      MI testbench
FL test.lst 2006/10/31.23:16:26 I.33
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/10/31.23:14:28 I.33 FL test.lst
d8 1
a8 1
      MI intcontrol     MI ram            MI rom            MI select         MI terminal
d16 2
a17 5
FL $XILINX/ISEexamples/cpu8080/common.vhd 2006/10/16.23:07:12 I.33
PH work/common 1162002890          FL $XILINX/ISEexamples/cpu8080/common.vhd \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794
PB work/common 1162002891          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1162002890 \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794
@


1.1.1.4
log
@8080 CPU project
@
text
@d1 3
a3 3
V3 56
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/11/08.22:19:48 I.33
PH work/vga_pckg 1163059899        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d6 1
a6 1
EN work/vga 1163059900             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d9 1
a9 1
AR work/vga/vga_arch 1163059901    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163059900 \
d11 1
a11 1
EN work/sync 1163059902            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d14 1
a14 1
AR work/sync/sync_arch 1163059903  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163059902
d17 1
a17 1
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/11/04.17:39:26 I.33
d20 2
a21 3
FL $XILINX/ISEexamples/cpu8080/vgachr.v 2006/11/09.00:42:54 I.33
MO work/terminal        FL $XILINX/ISEexamples/cpu8080/vgachr.v MI chrmemmap \
      MI ps2_kbd        MI scnrom         MI scnromu
d24 1
a24 3
MO work/scnrom          FL $XILINX/ISEexamples/cpu8080/vgachr.v
MO work/scnromu         FL $XILINX/ISEexamples/cpu8080/vgachr.v
FL $XILINX/ISEexamples/cpu8080/cpu8080_tbw.tfw 2006/11/04.23:09:58 I.33
d27 2
a28 2
FL test.lst 2006/11/04.23:37:34 I.33
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/11/08.21:58:30 I.33 FL test.rom
a37 8
FL test.rom 2006/11/05.09:53:26 I.33
FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd 2006/11/08.21:59:14 I.33
PH work/ps2_kbd_pckg 1163059896    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794 CD ps2_kbd
EN work/ps2_kbd 1163059897         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      PB ieee/std_logic_1164 1153526780 PB ieee/NUMERIC_STD 1153526794
AR work/ps2_kbd/arch 1163059898    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163059897
@


1.1.1.5
log
@8080 CPU project
@
text
@d2 2
a3 2
FL $XILINX/ISEexamples/cpu8080/vga.vhd 2006/11/15.08:45:56 I.33
PH work/vga_pckg 1163739302        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d6 1
a6 1
EN work/vga 1163739303             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d9 1
a9 1
AR work/vga/vga_arch 1163739304    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163739303 \
d11 1
a11 1
EN work/sync 1163739305            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d14 1
a14 1
AR work/sync/sync_arch 1163739306  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163739305
d17 1
a17 1
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/11/16.20:07:40 I.33
d20 1
a20 1
FL $XILINX/ISEexamples/cpu8080/vgachr.v 2006/11/15.08:51:40 I.33
d31 1
a31 1
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/11/16.21:40:32 I.33 FL test.rom
d41 1
a41 1
FL test.rom 2006/11/16.21:40:18 I.33
@


1.1.1.6
log
@8080 CPU project
@
text
@d1 1
a1 1
V3 53
d3 1
a3 1
PH work/vga_pckg 1163883883        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163883879 CD vga
EN work/vga 1163883884             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163883879
AR work/vga/vga_arch 1163883885    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163883884 \
d11 1
a11 1
EN work/sync 1163883886            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 5
a17 3
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163883879
AR work/sync/sync_arch 1163883887  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163883886
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/11/18.17:04:54 I.33
d27 1
a27 1
FL $XILINX/ISEexamples/cpu8080/cpu8080_tbw.tfw 2006/11/18.13:39:14 I.33
d30 2
a31 1
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/11/17.09:21:30 I.33 FL test.rom
d41 1
a41 1
FL test.rom 2006/11/17.09:21:06 I.33
d43 1
a43 1
PH work/ps2_kbd_pckg 1163883880    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d45 1
a45 1
EN work/ps2_kbd 1163883881         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d47 2
a48 2
AR work/ps2_kbd/arch 1163883882    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163883881
d50 1
a50 1
PH work/common 1163883878          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d52 1
a52 1
PB work/common 1163883879          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163883878 \
@


1.1.1.7
log
@8080 CPU project
@
text
@d3 1
a3 1
PH work/vga_pckg 1163918859        FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d5 2
a6 2
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163918855 CD vga
EN work/vga 1163918860             FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d8 2
a9 2
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163918855
AR work/vga/vga_arch 1163918861    FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/vga 1163918860 \
d11 1
a11 1
EN work/sync 1163918862            FL $XILINX/ISEexamples/cpu8080/vga.vhd LB unisim \
d13 3
a15 3
      PH unisim/VCOMPONENTS 1153527310 PB work/common 1163918855
AR work/sync/sync_arch 1163918863  FL $XILINX/ISEexamples/cpu8080/vga.vhd EN work/sync 1163918862
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/11/18.23:40:18 I.33
d25 1
a25 1
FL $XILINX/ISEexamples/cpu8080/cpu8080_tbw.tfw 2006/11/18.22:47:08 I.33
d40 1
a40 1
PH work/ps2_kbd_pckg 1163918856    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d42 1
a42 1
EN work/ps2_kbd 1163918857         FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
d44 2
a45 2
AR work/ps2_kbd/arch 1163918858    FL $XILINX/ISEexamples/cpu8080/ps2_kbd.vhd \
      EN work/ps2_kbd 1163918857
d47 1
a47 1
PH work/common 1163918854          FL $XILINX/ISEexamples/cpu8080/common.vhd \
d49 1
a49 1
PB work/common 1163918855          FL $XILINX/ISEexamples/cpu8080/common.vhd PH work/common 1163918854 \
@