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1.1
date	2006.10.06.20.07.59;	author samiam95124;	state Exp;
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1.1.1.1
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1.1
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@Initial revision
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@C:/Xilinx/verilog/src/glbl.v
C:/Xilinx/ISEexamples/cpu8080/cpu8080.v
C:/Xilinx/ISEexamples/cpu8080/testbench.v
C:/Xilinx/ISEexamples/cpu8080/cpu_tbw.tfw
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1.1.1.1
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@8080 CPU project
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1.1.1.2
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@8080 CPU project
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@a1 2
C:/Xilinx/ISEexamples/cpu8080/vga.vhd
C:/Xilinx/ISEexamples/cpu8080/vgachr.v
d4 1
a4 1
C:/Xilinx/ISEexamples/cpu8080/cpu8080_tbw.tfw
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1.1.1.3
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@8080 CPU project
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@a1 1
C:/Xilinx/ISEexamples/cpu8080/ps2_kbd.vhd
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