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1.1
date	2006.11.01.20.03.10;	author samiam95124;	state Exp;
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	1.1.1.1;
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1.1.1.1
date	2006.11.01.20.03.10;	author samiam95124;	state Exp;
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1.1.1.2
date	2006.11.11.12.06.04;	author samiam95124;	state Exp;
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1.1.1.3
date	2006.11.16.10.30.55;	author samiam95124;	state Exp;
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desc
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1.1
log
@Initial revision
@
text
@<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
     by the Xilinx ISE software.  Any direct editing or
     changes made to this file may result in unpredictable
     behavior or data corruption.  It is strongly advised that
     users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

</messages>
@


1.1.1.1
log
@8080 CPU project
@
text
@@


1.1.1.2
log
@8080 CPU project
@
text
@d8 1
a8 1
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
d14 1
a14 1
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
d17 1
a17 1
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
@


1.1.1.3
log
@8080 CPU project
@
text
@d8 1
a8 1
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
d14 1
a14 1
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
d17 1
a17 10
<msg type="warning" file="PhysDesignRules" num="372">Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
</msg>

<msg type="warning" file="PhysDesignRules" num="812">Dangling pin &lt;DOA5&gt; on block:&lt;adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A&gt;:&lt;RAMB16_RAMB16A&gt;.
</msg>

<msg type="warning" file="PhysDesignRules" num="812">Dangling pin &lt;DOA6&gt; on block:&lt;adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A&gt;:&lt;RAMB16_RAMB16A&gt;.
</msg>

<msg type="warning" file="PhysDesignRules" num="812">Dangling pin &lt;DOA7&gt; on block:&lt;adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A&gt;:&lt;RAMB16_RAMB16A&gt;.
@