head     1.1;
branch   1.1.1;
access   ;
symbols  arelease:1.1.1.1 avendor:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2008.08.05.19.44.15;  author fpga_is_funny;  state Exp;
branches 1.1.1.1;
next     ;
commitid        5d94898abca4567;

1.1.1.1
date     2008.08.05.19.44.15;  author fpga_is_funny;  state Exp;
branches ;
next     ;
commitid        5d94898abca4567;


desc
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1.1
log
@Initial revision
@
text
@-- VHDL Entity R65C02_TC.fsm_nmi.symbol
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:53:52 05.08.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

entity fsm_nmi is
   port( 
      CLK  : in     std_logic;
      NMIn : in     std_logic;
      RSTn : in     std_logic;
      NMI  : out    std_logic
   );

-- Declarations

end fsm_nmi ;

-- Jens-D. Gutschmidt     Project:  R65C02_TC  

-- scantara2003@@yahoo.de                       

-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log$                                                                                                                                       

--                                                                                                                                             

-- Title:  FSM for NMI  

-- Path:  R65C02_TC/fsm_nmi/fsm  

-- Edited:  by eda on 05 Aug 2008  

--
-- VHDL Architecture R65C02_TC.fsm_nmi.fsm
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:53:52 05.08.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
architecture fsm of fsm_nmi is

   type state_type is (
      idle,
      idle1,
      idle2,
      IMP
   );
 
   -- State vector declaration
   attribute state_vector : string;
   attribute state_vector of fsm : architecture is "current_state";

   -- Declare current and next state signals
   signal current_state : state_type;
   signal next_state : state_type;

   -- Declare any pre-registered internal signals
   signal NMI_cld : std_logic ;

begin

   -----------------------------------------------------------------
   clocked_proc : process ( 
      CLK,
      RSTn
   )
   -----------------------------------------------------------------
   begin
      if (RSTn = '0') then
         current_state <= idle;
         -- Default Reset Values
         NMI_cld <= '0';
      elsif (CLK'event and CLK = '1') then
         current_state <= next_state;
         -- Default Assignment To Internals
         NMI_cld <= '0';

         -- Combined Actions
         case current_state is
            when IMP => 
               NMI_cld <= '1';
            when others =>
               null;
         end case;
      end if;
   end process clocked_proc;
 
   -----------------------------------------------------------------
   nextstate_proc : process ( 
      NMIn,
      current_state
   )
   -----------------------------------------------------------------
   begin
      case current_state is
         when idle => 
            if (NMIn = '1') then 
               next_state <= idle1;
            else
               next_state <= idle;
            end if;
         when idle1 => 
            if (NMIn = '0') then 
               next_state <= idle2;
            else
               next_state <= idle1;
            end if;
         when idle2 => 
            if (NMIn = '0') then 
               next_state <= IMP;
            else
               next_state <= idle;
            end if;
         when IMP => 
            next_state <= idle;
         when others =>
            next_state <= idle;
      end case;
   end process nextstate_proc;
 
   -- Concurrent Statements
   -- Clocked output assignments
   NMI <= NMI_cld;
end fsm;
@


1.1.1.1
log
@loading source files "rtl" and "doc" STATE is BETA.
@
text
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