head 1.2; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.2 date 2008.04.17.18.39.34; author fpga_is_funny; state Exp; branches; next 1.1; commitid 5a04480797854567; 1.1 date 2008.04.08.20.07.57; author fpga_is_funny; state Exp; branches 1.1.1.1; next ; commitid 2b3f47fbcb9e4567; 1.1.1.1 date 2008.04.08.20.07.57; author fpga_is_funny; state Exp; branches; next ; commitid 2b3f47fbcb9e4567; desc @@ 1.2 log @Bugfixes for all relationchips with interrupts BRK, IRQ and NMI. The control for the stack pointer within fsm*s of BRK, IRQ and NMI was incorrect. The stack was allways growing up instead of growing down. The "B" status flag was never set within BRK. The relationchip between addresses and data while writing onto the stack was badly misalligned. @ text @-- VHDL Entity R6502_TC.Core.symbol -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 19:49:03 17.04.2008 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; entity Core is port( clk_clk_i : in std_logic; d_i : in std_logic_vector (7 downto 0); irq_n_i : in std_logic; nmi_n_i : in std_logic; rdy_i : in std_logic; rst_rst_n_i : in std_logic; so_n_i : in std_logic; a_o : out std_logic_vector (15 downto 0); d_o : out std_logic_vector (7 downto 0); rd_o : out std_logic; sync_o : out std_logic; wr_n_o : out std_logic; wr_o : out std_logic ); -- Declarations end Core ; -- Jens-D. Gutschmidt Project: R6502_TC -- scantara2003@@yahoo.de -- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG -- -- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version -- 3 of the License, or any later version. -- -- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A -- PARTICULAR PURPOSE. See the GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License along with this program. If not, see . -- -- CVS Revisins History -- -- $Log$ -- Title: Core of 6502 -- Path: R6502_TC/Core/struct -- Edited: by eda on 17 Apr 2008 -- -- VHDL Architecture R6502_TC.Core.struct -- -- Created: -- by - eda.UNKNOWN (ENTWICKL4-XP-PR) -- at - 19:49:03 17.04.2008 -- -- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13) -- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; library R6502_TC; architecture struct of Core is -- Architecture declarations -- Internal signal declarations signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0); signal adr_nxt_sp_o_i : std_logic_vector(15 downto 0); signal adr_o_i : std_logic_vector(15 downto 0); signal adr_pc_o_i : std_logic_vector(15 downto 0); signal adr_sp_o_i : std_logic_vector(15 downto 0); signal ch_a_o_i : std_logic_vector(7 downto 0); signal ch_b_o_i : std_logic_vector(7 downto 0); signal cout_pc_o_i : std_logic; signal d_alu_o_i : std_logic_vector(7 downto 0); signal d_regs_in_o_i : std_logic_vector(7 downto 0); signal d_regs_out_o_i : std_logic_vector(7 downto 0); signal fetch_o_i : std_logic; signal ld_o_i : std_logic_vector(1 downto 0); signal ld_pc_o_i : std_logic; signal ld_sp_o_i : std_logic; signal load_regs_o_i : std_logic; signal nmi_o_i : std_logic; signal offset_o_i : std_logic_vector(15 downto 0); signal q_a_o_i : std_logic_vector(7 downto 0); signal q_x_o_i : std_logic_vector(7 downto 0); signal q_y_o_i : std_logic_vector(7 downto 0); signal reg_0flag_core_o_i : std_logic; signal reg_0flag_o_i : std_logic; signal reg_1flag_o_i : std_logic; signal reg_3flag_core_o_i : std_logic; signal reg_6flag_o_i : std_logic; signal reg_7flag_core_o_i : std_logic; signal reg_7flag_o_i : std_logic; signal rst_rst_int_o_i : std_logic; signal sel_alu_as_o_i : std_logic; signal sel_alu_out_o_i : std_logic_vector(2 downto 0); signal sel_pc_as_o_i : std_logic; signal sel_pc_in_o_i : std_logic_vector(1 downto 0); signal sel_pc_val_o_i : std_logic_vector(1 downto 0); signal sel_rb_in_o_i : std_logic_vector(2 downto 0); signal sel_rb_out_o_i : std_logic_vector(2 downto 0); signal sel_reg_o_i : std_logic_vector(1 downto 0); signal sel_sp_as_o_i : std_logic; signal sel_sp_in_o_i : std_logic_vector(1 downto 0); signal sel_sp_val_o_i : std_logic_vector(1 downto 0); -- Component Declarations component ALU port ( ch_a_i : in std_logic_vector (7 downto 0); ch_b_i : in std_logic_vector (7 downto 0); reg_0flag_core_i : in std_logic ; reg_3flag_core_i : in std_logic ; reg_7flag_core_i : in std_logic ; sel_alu_as_i : in std_logic ; sel_alu_out_i : in std_logic_vector (2 downto 0); d_alu_o : out std_logic_vector (7 downto 0); reg_0flag_o : out std_logic ; reg_1flag_o : out std_logic ; reg_6flag_o : out std_logic ; reg_7flag_o : out std_logic ); end component; component RegBank_AXY port ( clk_clk_i : in std_logic ; d_regs_in_i : in std_logic_vector (7 downto 0); load_regs_i : in std_logic ; rst_rst_i : in std_logic ; sel_rb_in_i : in std_logic_vector (2 downto 0); sel_rb_out_i : in std_logic_vector (1 downto 0); sel_reg_i : in std_logic_vector (1 downto 0); d_regs_out_o : out std_logic_vector (7 downto 0); q_a_o : out std_logic_vector (7 downto 0); q_x_o : out std_logic_vector (7 downto 0); q_y_o : out std_logic_vector (7 downto 0) ); end component; component Reg_PC port ( adr_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic ; ld_i : in std_logic_vector (1 downto 0); ld_pc_i : in std_logic ; offset_i : in std_logic_vector (15 downto 0); rst_rst_i : in std_logic ; sel_pc_as_i : in std_logic ; sel_pc_in_i : in std_logic ; sel_pc_val_i : in std_logic_vector (1 downto 0); adr_nxt_pc_o : out std_logic_vector (15 downto 0); adr_pc_o : out std_logic_vector (15 downto 0); cout_pc_o : out std_logic ); end component; component Reg_SP port ( adr_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic ; ld_i : in std_logic_vector (1 downto 0); ld_sp_i : in std_logic ; rst_rst_i : in std_logic ; sel_sp_as_i : in std_logic ; sel_sp_in_i : in std_logic ; sel_sp_val_i : in std_logic ; adr_nxt_sp_o : out std_logic_vector (15 downto 0); adr_sp_o : out std_logic_vector (15 downto 0) ); end component; component fsm_core_V2_0 port ( adr_nxt_pc_i : in std_logic_vector (15 downto 0); adr_nxt_sp_i : in std_logic_vector (15 downto 0); adr_pc_i : in std_logic_vector (15 downto 0); adr_sp_i : in std_logic_vector (15 downto 0); clk_clk_i : in std_logic ; cout_pc_i : in std_logic ; d_alu_i : in std_logic_vector ( 7 downto 0 ); d_i : in std_logic_vector ( 7 downto 0 ); d_regs_out_i : in std_logic_vector ( 7 downto 0 ); irq_n_i : in std_logic ; nmi_i : in std_logic ; q_a_i : in std_logic_vector ( 7 downto 0 ); q_x_i : in std_logic_vector ( 7 downto 0 ); q_y_i : in std_logic_vector ( 7 downto 0 ); rdy_i : in std_logic ; reg_0flag_i : in std_logic ; reg_1flag_i : in std_logic ; reg_6flag_i : in std_logic ; reg_7flag_i : in std_logic ; rst_rst_n_i : in std_logic ; so_n_i : in std_logic ; a_o : out std_logic_vector (15 downto 0); adr_o : out std_logic_vector (15 downto 0); ch_a_o : out std_logic_vector ( 7 downto 0 ); ch_b_o : out std_logic_vector ( 7 downto 0 ); d_o : out std_logic_vector ( 7 downto 0 ); d_regs_in_o : out std_logic_vector ( 7 downto 0 ); fetch_o : out std_logic ; ld_o : out std_logic_vector ( 1 downto 0 ); ld_pc_o : out std_logic ; ld_sp_o : out std_logic ; load_regs_o : out std_logic ; offset_o : out std_logic_vector ( 15 downto 0 ); rd_o : out std_logic ; reg_0flag_o : out std_logic ; reg_1flag_o : out std_logic ; reg_3flag_o : out std_logic ; reg_7flag_o : out std_logic ; sync_o : out std_logic ; wr_n_o : out std_logic ; wr_o : out std_logic ; sel_alu_as_o_i : inout std_logic ; sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 ); sel_pc_as_o_i : inout std_logic ; sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 ); sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 ); sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 ); sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 ); sel_reg_o_i : inout std_logic_vector ( 1 downto 0 ); sel_sp_as_o_i : inout std_logic ; sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 ); sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 ) ); end component; component fsm_nmi port ( clk_clk_i : in std_logic ; fetch_i : in std_logic ; nmi_n_i : in std_logic ; rst_rst_n_i : in std_logic ; nmi_o : out std_logic ); end component; -- Optional embedded configurations -- pragma synthesis_off for all : ALU use entity R6502_TC.ALU; for all : RegBank_AXY use entity R6502_TC.RegBank_AXY; for all : Reg_PC use entity R6502_TC.Reg_PC; for all : Reg_SP use entity R6502_TC.Reg_SP; for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0; for all : fsm_nmi use entity R6502_TC.fsm_nmi; -- pragma synthesis_on begin -- ModuleWare code(v1.9) for instance 'U_5' of 'inv' rst_rst_int_o_i <= not(rst_rst_n_i); -- Instance port mappings. U_3 : ALU port map ( ch_a_i => ch_a_o_i, ch_b_i => ch_b_o_i, reg_0flag_core_i => reg_0flag_core_o_i, reg_3flag_core_i => reg_3flag_core_o_i, reg_7flag_core_i => reg_7flag_core_o_i, sel_alu_as_i => sel_alu_as_o_i, sel_alu_out_i => sel_alu_out_o_i, d_alu_o => d_alu_o_i, reg_0flag_o => reg_0flag_o_i, reg_1flag_o => reg_1flag_o_i, reg_6flag_o => reg_6flag_o_i, reg_7flag_o => reg_7flag_o_i ); U_2 : RegBank_AXY port map ( clk_clk_i => clk_clk_i, d_regs_in_i => d_regs_in_o_i, load_regs_i => load_regs_o_i, rst_rst_i => rst_rst_int_o_i, sel_rb_in_i => sel_rb_in_o_i, sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0), sel_reg_i => sel_reg_o_i, d_regs_out_o => d_regs_out_o_i, q_a_o => q_a_o_i, q_x_o => q_x_o_i, q_y_o => q_y_o_i ); U_0 : Reg_PC port map ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, ld_pc_i => ld_pc_o_i, offset_i => offset_o_i, rst_rst_i => rst_rst_int_o_i, sel_pc_as_i => sel_pc_as_o_i, sel_pc_in_i => sel_pc_in_o_i(0), sel_pc_val_i => sel_pc_val_o_i, adr_nxt_pc_o => adr_nxt_pc_o_i, adr_pc_o => adr_pc_o_i, cout_pc_o => cout_pc_o_i ); U_1 : Reg_SP port map ( adr_i => adr_o_i, clk_clk_i => clk_clk_i, ld_i => ld_o_i, ld_sp_i => ld_sp_o_i, rst_rst_i => rst_rst_int_o_i, sel_sp_as_i => sel_sp_as_o_i, sel_sp_in_i => sel_sp_in_o_i(0), sel_sp_val_i => sel_sp_val_o_i(0), adr_nxt_sp_o => adr_nxt_sp_o_i, adr_sp_o => adr_sp_o_i ); U_4 : fsm_core_V2_0 port map ( adr_nxt_pc_i => adr_nxt_pc_o_i, adr_nxt_sp_i => adr_nxt_sp_o_i, adr_pc_i => adr_pc_o_i, adr_sp_i => adr_sp_o_i, clk_clk_i => clk_clk_i, cout_pc_i => cout_pc_o_i, d_alu_i => d_alu_o_i, d_i => d_i, d_regs_out_i => d_regs_out_o_i, irq_n_i => irq_n_i, nmi_i => nmi_o_i, q_a_i => q_a_o_i, q_x_i => q_x_o_i, q_y_i => q_y_o_i, rdy_i => rdy_i, reg_0flag_i => reg_0flag_o_i, reg_1flag_i => reg_1flag_o_i, reg_6flag_i => reg_6flag_o_i, reg_7flag_i => reg_7flag_o_i, rst_rst_n_i => rst_rst_n_i, so_n_i => so_n_i, a_o => a_o, adr_o => adr_o_i, ch_a_o => ch_a_o_i, ch_b_o => ch_b_o_i, d_o => d_o, d_regs_in_o => d_regs_in_o_i, fetch_o => fetch_o_i, ld_o => ld_o_i, ld_pc_o => ld_pc_o_i, ld_sp_o => ld_sp_o_i, load_regs_o => load_regs_o_i, offset_o => offset_o_i, rd_o => rd_o, reg_0flag_o => reg_0flag_core_o_i, reg_1flag_o => open, reg_3flag_o => reg_3flag_core_o_i, reg_7flag_o => reg_7flag_core_o_i, sync_o => sync_o, wr_n_o => wr_n_o, wr_o => wr_o, sel_alu_as_o_i => sel_alu_as_o_i, sel_alu_out_o_i => sel_alu_out_o_i, sel_pc_as_o_i => sel_pc_as_o_i, sel_pc_in_o_i => sel_pc_in_o_i, sel_pc_val_o_i => sel_pc_val_o_i, sel_rb_in_o_i => sel_rb_in_o_i, sel_rb_out_o_i => sel_rb_out_o_i, sel_reg_o_i => sel_reg_o_i, sel_sp_as_o_i => sel_sp_as_o_i, sel_sp_in_o_i => sel_sp_in_o_i, sel_sp_val_o_i => sel_sp_val_o_i ); U_6 : fsm_nmi port map ( clk_clk_i => clk_clk_i, fetch_i => fetch_o_i, nmi_n_i => nmi_n_i, rst_rst_n_i => rst_rst_n_i, nmi_o => nmi_o_i ); end struct; @ 1.1 log @Initial revision @ text @d5 1 a5 1 -- at - 19:07:10 08.04.2008 d18 1 a18 1 nmi_i : in std_logic; a48 1 -- d51 1 a51 1 -- Edited: by eda on 08 Apr 2008 d57 1 a57 1 -- at - 19:07:10 08.04.2008 d83 1 d88 1 d205 1 d232 9 d249 1 d328 1 a328 1 nmi_i => nmi_i, d345 1 d371 8 @ 1.1.1.1 log @First Revision After the successfully functional test with a SoC of an APPLE][+, I corrected the wrong CVS log entry "$log$" to "$Log$" into all VHDL files. I hope this will not have a bad impact for cpu6502_tc...smile The CVS history in the VHDL files is fine now. @ text @@