head     1.1;
branch   1.1.1;
access   ;
symbols  start:1.1.1.1 thorn_aitch:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2003.07.12.13.23.06;  author thorn_aitch;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2003.07.12.13.23.06;  author thorn_aitch;  state Exp;
branches ;
next     ;


desc
@@



1.1
log
@Initial revision
@
text
@/*
===================
test source program
testdiv.src

Jan.28 2003
===================

address           size wait width device
00000000-00001FFF  8K  0    32    ROM
00010000-00011FFF  8K  3    32    ROM
00020000-00021FFF  8K  0    16    ROM
00030000-00031FFF  8K  3    16    ROM
ABCD0000-ABCD0003   4  3    32    PIO
ABCD0100-ABCD0103   4  3    32    UART
ABCD0200-ABCD0207   8  3    32    SYS
FFFCE000-FFFCFFFF  8K  0    32    RAM
FFFDE000-FFFDFFFF  8K  3    32    RAM
FFFEE000-FFFEFFFF  8K  0    16    RAM
FFFFE000-FFFFFFFF  8K  3    16    RAM
*/

.equ _rom0, 0x00000000
.equ _rom1, 0x00010000
.equ _rom2, 0x00020000
.equ _rom3, 0x00030000
.equ _pio,  0xabcd0000
.equ _uart, 0xabcd0100
.equ _sys,  0xabcd0200
.equ _ram0, 0xfffce000
.equ _ram1, 0xfffde000
.equ _ram2, 0xfffee000
.equ _ram3, 0xffffe000

.org _rom0
.long _rom0 + _init - _rom0
.long _ram0 + 0x02000

.org 0x0400
 
/**************
 Initialization
 **************/
_init:
_start:
 mov    #0, r14
_test:
 mov.l  _pfail, r13 !fail address
 bra    _testgo
 nop
_pfail: .long _fail

_testgo:
 mov.l  _ptestvalue, r9
/******************************************
 Unsigned R1(32bit) / R0(16bit) -> R1(16bit)
 ******************************************/
 mov.l @@r9+, r1
 mov.l @@r9+, r0
 div0u
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 div1 r0, r1
 rotcl r1
 mov.l @@r9+, r2
 cmp/eq r2, r1
 bt     .+6
 jmp    @@r13
 nop
/**********************************************
 Unsigned R1:R2(64bit) / R0(32bit) -> R2(32bit)
 **********************************************/
 mov.l @@r9+, r1
 mov.l @@r9+, r2
 mov.l @@r9+, r0
 div0u
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1

 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1

 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1

 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1
 rotcl r2
 div1  r0,r1

 rotcl r2
 mov.l @@r9+, r3
 cmp/eq r3, r2
 bt     .+6
 jmp    @@r13
 nop
/*****************************************
 Signed R1(16bit) / R0(16bit) -> R1(16bit)
 *****************************************/
 mov.l @@r9+, r1
 mov.l @@r9+, r0
 div0s r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 div1  r0, r1
 mov.l @@r9+, r2
 cmp/eq r2, r1
 bt     .+6
 jmp    @@r13
 nop
/*****************************************
 Signed R2(32bit) / R0(32bit) -> R2(32bit)
 *****************************************/
 mov.l @@r9+, r1
 mov.l @@r9+, r2
 mov.l @@r9+, r0
 div0s r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1

 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1

 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1
 rotcl r2
 div1  r0, r1

 rotcl r2
 mov.l @@r9+, r3
 cmp/eq r3, r2
 bt     .+6
 jmp    @@r13
 nop
!----
 bra    _testfinish
 nop
!----
 .align 4
_ptestvalue: .long _testvalue
_testvalue :
!----32 by 16 unsigned
 .long 0x71c638e4
 .long 0xaaaa0000
 .long 0xaaacaaaa
!----64 by 32 unsigned
 .long 0x0b00ea4e
 .long 0x242d2080
 .long 0x9abcdef0
 .long 0x12345678
!----16 by 16 signed
 .long 0xfffffeff !=ffffff00-1
 .long 0x00100000
 .long 0x000ffff7
!----32 by 32 signed
 .long 0xffffffff
 .long 0xdb97530f
 .long 0xfffffffe
 .long 0x12345678

_testfinish:
/*********************************************************
 Move to another Next ROM area to check hardware operation
 *********************************************************/
 mov.l _pbranch_table, r13
 add r14, r13
 mov.l @@r13, r12
 jmp @@r12
 add #4, r14
.align 4
_pbranch_table: .long _branch_table
_branch_table:
 .long _rom1+_test
 .long _rom2+_test
 .long _rom3+_test
 .long _rom0+_pass

/**************
 Congraturation
 **************/
_pass:
 mov.l _ppass_value, r0
 mov.l _ppass_value, r1
 mov.l r0, @@r1
 bra   _pass
 nop
.align 4
_ppass_value: .long 0x12345678

/**********
 You Failed
 **********/
_fail:
 mov.l _pfail_value, r0
 mov.l _pfail_value, r1
 bra   _fail
 nop
.align 4
_pfail_value: .long 0x88888888

.end
@


1.1.1.1
log
@First Release
@
text
@@