head 1.5; access; symbols; locks; strict; comment @# @; 1.5 date 2005.09.23.23.30.24; author zuofu; state Exp; branches; next 1.4; commitid 9364334900b4567; 1.4 date 2005.09.23.22.05.55; author zuofu; state Exp; branches; next 1.3; commitid 784c43347c414567; 1.3 date 2005.09.23.21.35.27; author zuofu; state Exp; branches; next 1.2; commitid 6e75433475134567; 1.2 date 2005.09.23.21.17.15; author zuofu; state Exp; branches; next 1.1; commitid 6ae3433470ba4567; 1.1 date 2005.09.16.20.48.19; author zuofu; state Exp; branches; next ; commitid 243432b2f904567; desc @@ 1.5 log @more work on GPU core @ text @--ECE395 GPU: --GPU Core Intermediate Block --===================================================== --Designed by: --Zuofu Cheng --James Cavanaugh --Eric Sands -- --of the University of Illinois at Urbana Champaign --under the direction of Dr. Lippold Haken --==================================================== -- --Heavily based off of HDL examples provided by XESS Corporation --www.xess.com -- --Based in part on Doug Hodson's work which in turn --was based off of the XSOC from Gray Research LLC. -- -- --release under the GNU General Public License --and kindly hosted by www.opencores.org library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.common.all; use WORK.sdram.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; package GPU_core_pckg is component GPU_core generic( FREQ : natural := 50_000; -- operating frequency in KHz DATA_WIDTH : natural := 16; -- host & SDRAM data width HADDR_WIDTH : natural := 23 -- host-side address width ); port( clk : in std_logic; -- master clock rst : in std_logic; -- reset for this entity rd1 : out std_logic; -- initiate read operation wr1 : out std_logic; -- initiate write operation opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked) done1 : in std_logic; -- read or write operation is done rddone1 : in std_logic; -- read operation is done rdPending1 : in std_logic; -- read operation is not done hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM start_read : in std_logic; source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0); target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0); end_address : in std_logic_vector(HADDR_WIDTH-1 downto 0) ); end component GPU_core; end package GPU_core_pckg; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.fifo_cc_pckg.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity GPU_core is generic( FREQ : natural := 50_000; -- operating frequency in KHz DATA_WIDTH : natural := 16; -- host & SDRAM data width HADDR_WIDTH : natural := 23 -- host-side address width ); Port ( clk : in std_logic; -- master clock rst : in std_logic; -- reset for this entity rd1 : out std_logic; -- initiate read operation wr1 : out std_logic; -- initiate write operation opBegun1 : in std_logic; -- read/write/self-refresh op begun (clocked) done1 : in std_logic; -- read or write operation is done rddone1 : in std_logic; -- read operation is done rdPending1 : in std_logic; -- read operation is not done hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM hDIn1 : out std_logic_vector(DATA_WIDTH-1 downto 0); -- data to dualport to SDRAM hDOut1 : in std_logic_vector(DATA_WIDTH-1 downto 0); -- data from dualport to SDRAM start_read : in std_logic; source_address : in std_logic_vector(HADDR_WIDTH-1 downto 0); target_address : in std_logic_vector(HADDR_WIDTH-1 downto 0); end_address : in std_logic_vector(HADDR_WIDTH-1 downto 0) ); end GPU_core; architecture Behavioral of GPU_core is -------------------------------------------------------------------------------------------------------------- -- Signal Declarations -------------------------------------------------------------------------------------------------------------- type state_type is (halt, read0, read1, read2, read3, write0, write1, write2); signal current_state,next_state : state_type; signal address : std_logic_vector(HADDR_WIDTH-1 downto 0); signal output : std_logic_vector(15 downto 0); --signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0); signal wr_q, rd_q, full_q, empty_q : std_logic; signal datain_q, dataout_q : std_logic_vector(DATA_WIDTH-1 downto 0); signal level_q : std_logic_vector(7 downto 0); begin -------------------------------------------------------------------------------------------------------------- -- Beginning of Submodules -- All instances of submodules and signals associated with them -- are declared within. Signals not directly associated with -- submodules are declared elsewhere. -- -------------------------------------------------------------------------------------------------------------- u1 : fifo_cc port map( clk=>clk, rst=>rst, rd=>rd_q, wr=>wr_q, data_in=>datain_q, data_out=>dataout_q, full=>full_q, empty=>empty_q, level=>level_q ); -------------------------------------------------------------------------------------------------------------- -- End of Submodules -------------------------------------------------------------------------------------------------------------- -- Begin GPUCore Module -- Process that puts data into the FIFO whenever on rising edge of clk when rdDone1 is high getdata : process ( clk, rdDone1, hDOut1) begin if rising_edge(clk) then if rdDone1 = '1' then wr_q <= '1'; datain_q <= hDOut1; else wr_q <= '0'; end if; -- if rdDone1 = '0' and done1 = '1' then -- rd_q <= '1'; -- hDIn1 <= dataout_q; -- else -- rd_q <= '0'; -- end if; end if; end process; -- Main state machine sequential process sync_proc : process(clk, rst) begin if (rst = '1') then current_state <= halt; elsif rising_edge(clk) then current_state <= next_state; end if; end process; -- Main state machine combinatoric process comb_proc : process(current_state) begin case current_state is when halt => rd1 <= '0'; address <= source_address; hAddr1 <= "00000000000000000000000"; if start_read = '1' then next_state <= read0; end if; when read0 => rd1 <= '1'; hAddr1 <= address; -- EXIT CONDITION if end_address = address then next_state <= read3; elsif opBegun1 = '1' then next_state <= read1; end if; when read1 => rd1 <= '1'; address <= address + 1; hAddr1 <= address; -- EXIT CONDITION if end_address = address then next_state <= read3; elsif opBegun1 = '1' then next_state <= read2; end if; when read2 => rd1 <= '1'; address <= address + 1; hAddr1 <= address; -- EXIT CONDITION if end_address = address then next_state <= read3; elsif opBegun1 = '1' then next_state <= read1; end if; when read3 => rd1 <= '0'; address <= target_address; if rdPending1 = '0' and done1 = '0' then next_state <= write0; end if; when write0 => wr1 <= '1'; hAddr1 <= address; rd_q <= '1'; hDIn1 <= dataout_q; if opBegun1 = '1' then next_state <= write1; end if; when write1 => wr1 <= '1'; hAddr1 <= address; address <= address + 1; rd_q <= '1'; hDin1 <= dataout_q; if (empty_q = '0' and opBegun1 = '1') then next_state <= write2; elsif (empty_q = '1') then next_state <= halt; end if; when write2 => wr1 <= '1'; hAddr1 <= address; address <= address + 1; rd_q <= '1'; hDin1 <= dataout_q; if (empty_q = '0' and opBegun1 = '1') then next_state <= write1; elsif (empty_q = '1') then next_state <= halt; end if; end case; end process; end Behavioral; @ 1.4 log @fixed up a lot of code, logic for GPU Core is still broken... @ text @d108 1 a108 1 signal stop_address : std_logic_vector(HADDR_WIDTH-1 downto 0); d151 6 a156 6 if rdDone1 = '0' and done1 = '1' then rd_q <= '1'; hDIn1 <= dataout_q; else rd_q <= '0'; end if; d178 1 d238 4 d243 12 d256 5 d262 5 @ 1.3 log @fixed small bug in interlacing logic @ text @d48 1 d56 2 a57 2 size : in std_logic_vector(9 downto 0) ); d85 1 d99 6 a104 2 type my_state is (wait4Go, getLine, writeLine); signal state : my_state; d115 24 d140 2 a141 1 statemachineread : process() d143 7 d151 23 a173 1 case state is d180 1 a180 1 state <= readBegin; d183 5 a187 2 when readBegin => d190 3 a192 3 state <= readEnd; elsif opBegun = '1' then state <= read1; a194 3 rd1 <= '1'; hAddr1 <= address; a196 7 -- EXIT CONDITION if end_address = address then state <= readEnd; elsif opBegun = '1' then state <= read2; end if; a200 2 when read2 => d203 3 a205 3 state <= readEnd; elsif opBegun = '1' then state <= read1; d208 2 a212 2 when readEnd => d214 5 a218 2 if rdPending = '0' and done1 = '0' then state <= writeBegin; d220 2 d226 5 a230 1 when writeBegin => d240 2 a243 9 getdata : process ( clk, rdDone1, hDOut1) begin if rising_edge(clk) then if rdDone1 = '1' then wr_q <= '1'; datain_q <= hDOut1; else wr_q <= '0'; end if; d245 2 a246 21 if rdDone1 = '0' and done1 = '1' then rd_q <= '1'; hDIn1 <= dataout_q; else rd_q <= '0'; end if; end if; end process; u1 : fifo_cc port map( clk=>clk, rst=>rst, rd=>rd_q, wr=>wr_q, data_in=>datain_q, data_out=>dataout_q, full=>full_q, empty=>empty_q, level=>level_q ); @ 1.2 log @uploaded correct GPU core hdl @ text @d1 22 a59 22 -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 21:06:27 09/14/05 -- Design Name: -- Module Name: GPU_core - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- a109 76 -- getstate : process (clk, rst, state) -- begin -- -- if rst = '0' then -- state <= wait4Go; -- elsif state = wait4Go then -- if start_read = '1' then -- state <= getLine; -- end if; -- end if; -- -- end process; -- getandwritedata : process(clk, rst, start_read, rdPending1, done1, dataout_q, opBegun1, datain_q) -- begin -- if rst = '1' then -- state <= wait4Go; -- wr_q <= '0'; -- rd_q <= '0'; -- wr1 <= '0'; -- rd1 <= '0'; -- hAddr1 <= (others => '0'); -- else -- -- case state is -- when wait4Go => -- if start_read = '1' then -- state <= getLine; -- end if; -- -- when writeLine => -- address <= target_address; -- stop_address <= size + target_address; -- if rising_edge(clk) then -- -- check to see if the Line is done being written into SDRAM -- if address = stop_address and -- opBegun1 = '0' and done1 = '0' then -- state <= wait4Go; -- end if; -- -- rd_q <= '1'; -- read from the queue -- hDIn1 <= dataout_q; -- data from the queue to SDRAM -- wr1 <= '1'; -- write to the SDRAM -- hAddr1 <= address; -- at target_address -- -- if done1 = '1' then -- address <= address + 1; -- end if; -- -- end if; -- -- when getLine => -- address <= source_address; -- stop_address <= size + source_address; -- if rising_edge(clk) then -- -- -- check to see if the Line is loaded into the queue -- if address = stop_address and -- entire line has been read -- rdPending1 = '0' and done1 = '0' then -- read operation is complete -- state <= writeLine; -- end if; -- -- wr_q <= '1'; -- datain_q <= hDOut1; -- rd1 <= '1'; -- hAddr1 <= address; -- -- if done1 = '1' then -- address <= address + 1; -- end if; -- -- end if; -- end case; -- end if; -- end process; a200 34 -- getLinedata : process( clk, rst, rdPending1, done1, opBegun1, datain_q) -- begin -- if rst = '1' then -- state <= wait4Go; -- wr_q <= '0'; -- rd_q <= '0'; -- wr1 <= '0'; -- rd1 <= '0'; -- count <= (others <= '0'); -- elsif state <= getLine then -- address <= source_address; -- if rising_edge(clk) then -- -- -- check to see if the Line is loaded into the queue -- if count = size and -- entire line has been read -- rdPending = '0' and done1 = '0' then -- read operation is complete -- state <= writeLine; -- end if; -- -- wr_q <= '1'; -- datain_q <= hDOut1; -- rd1 <= 1; -- hAddr1 <= address; -- -- if done1 = '1' then -- count <= count + 1; -- address <= address + 1; -- end if; -- -- end if; -- end if; -- end process; @ 1.1 log @added gpu_core @ text @a0 23 --ECE395 GPU Core: --===================================================== --Designed by: --Zuofu Cheng --James Cavanaugh --Eric Sands -- --of the University of Illinois at Urbana Champaign --under the direction of Dr. Lippold Haken --==================================================== -- --Heavily based off of HDL examples provided by XESS Corporation --www.xess.com -- --Based in part on Doug Hodson's work which in turn --was based off of the XSOC from Gray Research LLC. -- -- --release under the GNU General Public License --and kindly hosted by www.opencores.org d6 2 d11 3 a13 2 package gpu_core_pckg is component gpu_core d21 1 a21 1 rst : in std_logic; -- reset for this entity d24 1 a24 1 opBegun : in std_logic; -- read/write/self-refresh op begun (clocked) d26 2 a27 2 rdDone1 : in std_logic; hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM d30 4 a33 4 CacheDIn : inout std_logic_vector(15 downto 0); -- data to SRAM Cache CacheAddr : out std_logic_vector(14 downto 0); -- address to SRAM Cache cread : out std_logic; -- cache read active low cwrite : out std_logic -- cache write active low d35 4 a38 2 end component gpu_core; end package gpu_core_pckg; d40 22 a61 5 library IEEE, UNISIM; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; use UNISIM.VComponents.all; use WORK.common.all; d64 6 d71 1 a71 1 entity gpu_core is d79 1 a79 1 rst : in std_logic; -- reset for this entity d82 1 a82 1 opBegun : in std_logic; -- read/write/self-refresh op begun (clocked) d84 2 a85 2 rdDone1 : in std_logic; hAddr1 : out std_logic_vector(HADDR_WIDTH-1 downto 0); -- address to SDRAM d88 4 a91 4 CacheDIn : inout std_logic_vector(15 downto 0); -- data to SRAM Cache CacheAddr : out std_logic_vector(14 downto 0); -- address to SRAM Cache cread : out std_logic; -- cache read active low cwrite : out std_logic -- cache write active low d93 1 a93 1 end gpu_core; d95 1 a95 1 architecture Behavioral of gpu_core is d97 2 d100 3 a102 5 signal source_address : std_logic_vector(HADDR_WIDTH-1 downto 0); signal target_address : std_logic_vector(HADDR_WIDTH-1 downto 0); signal wordread : std_logic_vector(5 downto 0); signal writemode : std_logic; signal linecache : std_logic_vector(255 downto 0); d104 3 d108 1 d110 81 a190 1 begin d192 2 a193 4 cread <= '1'; cwrite <= '1'; CacheDIn <= (others => 'Z'); CacheAddr <= "000000000000000"; d195 81 d277 1 a277 1 -- process (clk, rst, writemode, done1, rddone1) a278 1 -- if (rising_edge (clk)) then d280 15 a294 5 -- source_address <= "00000010010011000000000"; -- target_address <= "00000000000000000000000"; -- wordread <= "000000"; -- writemode <= '0'; -- end if; d296 4 a299 4 -- if writemode = '0' then --reading a line -- rd1 <= '1'; -- wr1 <= '0'; -- hAddr1 <= source_address; d301 4 a304 4 -- if opBegun = '1' and (wordread /= "010000") then -- source_address <= source_address + 1; -- wordread <= wordread + 1; -- end if; a305 8 -- if rdDone1 = '1' then -- linecache <= linecache(239 downto 0) & "0000000000000000"; -- linecache (15 downto 0) <= hDOut1; -- end if; -- -- if wordread = "010000" and rdDone1 = '0' then -- wordread <= "000000"; -- writemode <= '1'; a306 26 -- else -- wr1 <= '1'; -- rd1 <= '0'; -- hDin1 <= linecache (255 downto 239); -- hAddr1 <= target_address; -- if (opBegun = '1' and wordread /= "010000") then -- linecache <= linecache(239 downto 0) & "0000000000000000"; -- target_address <= target_address + 1; -- wordread <= wordread + 1; -- end if; -- ---- if wordread = "000000" then ---- ---- end if; ---- ---- if wordread = "010000" then ---- wr1 <= '0'; ---- end if; ---- -- -- wordread <= wordread + 1; -- --end if; -- if wordread = "010000" and Done1 = '0' then -- wordread <= "000000"; -- writemode <= '0'; -- end if; -- d308 15 a322 2 -- end if; -- end process; @