USB Host Controller
This USB controller will support one of the multiple modes of data transfer, that is isochronous data transfer. Isochronous transfers send or received data streams in realtime with guaranteed bus bandwidth but without any reliability. In general these transfer types are used for audio and video devices.
The USB controller will properly
support the configuration process whereby the device is assigned an address. It
then monitor the bus for packets addressed to itself and handle the transfer of
data to host machine. Data must be packaged into packets and transmitted to the
host. Meanwhile, incoming packets must be verified for validity through the use
of 5 and 16-bit CRCs and 1’s complement checkbits. The controller will be able
to handle two types of transactions, meaning it must respond to two packets. The
first packet is a SETUP packet. When a SETUP packet is received, one expected to
receive an 8 byte data packet and the chip have to respond with an acknowledge
signal ( ACK ). The 8 byte data packet contains the newly assigned address. We called it
configuration process. The second packet is an IN packet. When an IN packet is
received from the host, the controller checks to see if the address matches the
chip’s assigned address. If a match is detected, we send a data packet. We
called it application process.
The design process of this chip
uses finite state machine ( FSM ) method based on top-down modular design
approach as shown below. Its VHDL code is described either at behavioral or
structural level. Then we simulate and verify each module we have designed. The
final step is to synthesize its logic circuit and implement its hardware. So
far, We have designed and verified several modules that worked properly.
These modules are :
This module converts the serial
input from the host. Remember, all data must be packaged into packet that
suitable for USB protocol. Its implementation uses a 8 bit shift register
This module determines whether
the incoming packet is setup packet or in packet. This information can be known
by detecting the type and check bits of the packet. Clearly, we may use two
comparator to handle each packet.
The USB
specification calls for the use of Cyclic Redundancy Checksums ( CRC ) to
protect all non PID fields in token and data packets from errors during
transmission. The USB specification lists two generator polynomials, one for
token and the other for data packets. The generator polynomial for tokens is x5
+ x2 + x0 while the generator poynomial for data packets
is x16 + x15 + x2 + x0. Since the
remainder is always of smaller degree than the generator polynomial, the token
CRC is a bit pattern and the CRC is a 16 bit pattern. Its implementation uses
XOR gates and D-flip-flops.
When the incoming packet is a
setup packet, then we have to send 0000000 as an input to the 7 bit comparator.
If a match signal is detected, then address register will save the address. To
realize this circuit, we need latch and comparator
When a SETUP packet is received, one expect to receive an 8 byte data packet, and then we have to respond with an ACK. The 8 bytes data packet contains the newly assigned address.
When the in packet from host was received properly, the controller have to respond it by sending the data requested by host. As mention above, this data must be packaged into packet and then send to host serially. We using an 8 bit register and multiplexer to realize this circuit.
All of this modules can be created using Alliance tools
Please contact us for further
information about this project.
Developers :