Description

PWM/Timer/Counter (PTC) IP core is a user-programmable PWM, Timer and Counter controller. Its use is to implement functions like Pulse Width Modulation (PWM), timer and counter facilities.

Features

The following lists the main features of PTC IP core:

• 32-bit counter/timer facility
• single-run or continues run of PTC counter
• Programmable PWM mode
• System clock and external clock sources for timer functionality
• HI/LO Reference and Capture registers
• Three-state control for PWM output driver
• PWM/Timer/Counter functionalities can cause an interrupt to the CPU
• WISHBONE SoC Interconnection Rev. B compliant interface

More information about the WISHBONE SoC and a full specification can be found here.

For further information, questions and general discussions related to the PTC core, please visit the Cores Mailing list. To subscribe to the Cores mailing list go to the Mailing-Lists page and select cores from the pull down menu at the end of the page. Enter your email address and click "Do it!"

Status

• Verilog RTL and verification suite under development
• The Specification is complete: ptc_spec.pdf (about 2.3MB)

Downloading

To get a snapshot of the latest release, please go to CVSget (from main OpenCores web page) and enter "ptc" as Module Name (without quotes). This will create a gzip'ed tar file of the entire PTC core.

Author / Maintainer

Damjan Lampret
lampret@opencores.org_NOSPAM

Feel free to send me comments, suggestions and bug reports.

Change Log

• 22/3/2001 DL Preliminary Spec available
• 21/3/2001 DL Initial web page