(See change Log at bottom of page for changes/updates)

Description:

Simple DES core.

Motivation

• A simple DES core
• Fast and Small Version
• Open Source

Compatibility

I believe that the core complies to NIST-800-17. However, there has been no formal third party verification.

The official NIST specification can be downloaded here: 800-17.pdf

Performance

 Two implementations are provided:

1) Area Optimized

This is a sequential implementation and needs 16 cycles to complete  a full encryption/decryption cycle.

• 0.18u UMC ASIC process: >155Mhz 3K Gates
• Altera APEX 20KE-1: 1106 lcells >27MHz
• Altera FLEX 10K50E-1: 1283 lcells >43MHz

2) Performance Optimized

This is a pipelined implementation that has a 16 cycle pipeline (plus 1 input and 1 output register). It can perform a complete  encryption/decryption every cycle.

• 0.18u UMC ASIC process: >290Mhz 28K Gates
• Altera APEX 20KE-1: 6688 lcells >53MHz
• Altera FLEX 10K130E-1: 6485 lcells >76 Mhz

Implementing the Core

Nothing special about implementing the core.

Status

Second Release: Added Encrypt/Decrypt input (Thanks to Mark Cynar for providing the code); Changed Directory Structure; Improved tetst benches.

Download

To get a tared and gziped snapshot from CVS click here, or go to the CVS info page.

To-Do

Author / Maintainer

I have been doing ASIC design, verification and synthesis for over 15 years. I hope you find this cores useful. Please send me a note if you intend to use it  !

Rudolf Usselmann
rudi@asics.ws_NOSPAM
www.asics.ws

Feel free to send me comments, suggestions and bug reports.

Change Log

10/6/2001 RU - Updated Directory Structure, added encrypt/decrypt, improved test bench

9/14/2000 RU - Initial release