Re: [fpu] FRem

[Rudolf Usselmann <rudi@asics.ws>]

on 8/28/00 13:00, Jamil Khatib at jamilkhatib75@yahoo.com wrote:
> What I am not sure about is if I add mod operator to
> the fdiv code what is going to happen after synthesis
> (i.e. which approach will be used )

Depends what synthesis tool you use and what libraries
come with it. Synopsys design compiler usually comes
with a Design Ware library. I don't know if it has
a mod operator or not, and if it does how it is implemented.

I don't see the use of this, as you can not provide the
result of a fdiv and the remainder at the same time, without
modifying the architecture of the FPU.

Why don't you get the basic function working first, and then
try to add additional features.

> anyhow what is the mod or rem operator in verilog?

Same as it is in any other programming language: '%'

> Regards
> Jamil Khatib
> 

rudi